Kirill A. Shutemov 4074ca7d8a x86/mm: Move LDT remap out of KASLR region on 5-level paging ... commit d52888aa2753e3063a9d3a0c9f72f94aa9809c15 upstream On 5-level paging the LDT remap area is placed in the middle of the KASLR randomization region and it can overlap with the direct mapping, the vmalloc or the vmap area. The LDT mapping is per mm, so it cannot be moved into the P4D page table next to the CPU_ENTRY_AREA without complicating PGD table allocation for 5-level paging. The 4 PGD slot gap just before the direct mapping is reserved for hypervisors, so it cannot be used. Move the direct mapping one slot deeper and use the resulting gap for the LDT remap area. The resulting layout is the same for 4 and 5 level paging. [ tglx: Massaged changelog ] Fixes: f55f0501cb ("x86/pti: Put the LDT in its own PGD if PTI is on") Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andy Lutomirski <luto@kernel.org> Cc: bp@alien8.de Cc: hpa@zytor.com Cc: dave.hansen@linux.intel.com Cc: peterz@infradead.org Cc: boris.ostrovsky@oracle.com Cc: jgross@suse.com Cc: bhe@redhat.com Cc: willy@infradead.org Cc: linux-mm@kvack.org Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181026122856.66224-2-kirill.shutemov@linux.intel.com Signed-off-by: Sasha Levin <sashal@kernel.org>		2018-11-27 16:13:08 +01:00
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i386
x86_64	x86/mm: Move LDT remap out of KASLR region on 5-level paging	2018-11-27 16:13:08 +01:00
00-INDEX
amd-memory-encryption.txt
boot.txt
earlyprintk.txt
entry_64.txt
exception-tables.txt
intel_mpx.txt
intel_rdt_ui.txt
kernel-stacks
microcode.txt
mtrr.txt
orc-unwinder.txt
pat.txt
protection-keys.txt
pti.txt
tlb.txt
topology.txt
usb-legacy-support.txt
zero-page.txt