e40678559f
Flushing the cache is needed for the hardware to see the idmap table and therefore can be done at init time. On ARMv7 it is not necessary to flush L2 so flush_cache_louis() is used here instead. There is no point flushing the cache in setup_mm_for_reboot() as the caller should, and already is, taking care of this. If switching the memory map requires a cache flush, then cpu_switch_mm() already includes that operation. What is not done by cpu_switch_mm() on ASID capable CPUs is TLB flushing as the whole point of the ASID is to tag the TLBs and avoid flushing them on a context switch. Since we don't have a clean ASID for the identity mapping, we need to flush the TLB explicitly in that case. Otherwise this is already performed by cpu_switch_mm(). Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
120 lines
3 KiB
C
120 lines
3 KiB
C
#include <linux/kernel.h>
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#include <asm/cputype.h>
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#include <asm/idmap.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/sections.h>
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#include <asm/system_info.h>
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pgd_t *idmap_pgd;
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#ifdef CONFIG_ARM_LPAE
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static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end,
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unsigned long prot)
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{
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pmd_t *pmd;
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unsigned long next;
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if (pud_none_or_clear_bad(pud) || (pud_val(*pud) & L_PGD_SWAPPER)) {
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pmd = pmd_alloc_one(&init_mm, addr);
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if (!pmd) {
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pr_warning("Failed to allocate identity pmd.\n");
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return;
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}
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pud_populate(&init_mm, pud, pmd);
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pmd += pmd_index(addr);
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} else
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pmd = pmd_offset(pud, addr);
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do {
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next = pmd_addr_end(addr, end);
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*pmd = __pmd((addr & PMD_MASK) | prot);
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flush_pmd_entry(pmd);
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} while (pmd++, addr = next, addr != end);
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}
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#else /* !CONFIG_ARM_LPAE */
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static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end,
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unsigned long prot)
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{
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pmd_t *pmd = pmd_offset(pud, addr);
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addr = (addr & PMD_MASK) | prot;
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pmd[0] = __pmd(addr);
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addr += SECTION_SIZE;
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pmd[1] = __pmd(addr);
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flush_pmd_entry(pmd);
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}
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#endif /* CONFIG_ARM_LPAE */
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static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
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unsigned long prot)
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{
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pud_t *pud = pud_offset(pgd, addr);
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unsigned long next;
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do {
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next = pud_addr_end(addr, end);
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idmap_add_pmd(pud, addr, next, prot);
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} while (pud++, addr = next, addr != end);
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}
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static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
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{
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unsigned long prot, next;
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prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
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if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
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prot |= PMD_BIT4;
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pgd += pgd_index(addr);
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do {
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next = pgd_addr_end(addr, end);
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idmap_add_pud(pgd, addr, next, prot);
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} while (pgd++, addr = next, addr != end);
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}
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extern char __idmap_text_start[], __idmap_text_end[];
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static int __init init_static_idmap(void)
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{
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phys_addr_t idmap_start, idmap_end;
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idmap_pgd = pgd_alloc(&init_mm);
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if (!idmap_pgd)
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return -ENOMEM;
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/* Add an identity mapping for the physical address of the section. */
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idmap_start = virt_to_phys((void *)__idmap_text_start);
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idmap_end = virt_to_phys((void *)__idmap_text_end);
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pr_info("Setting up static identity map for 0x%llx - 0x%llx\n",
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(long long)idmap_start, (long long)idmap_end);
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identity_mapping_add(idmap_pgd, idmap_start, idmap_end);
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/* Flush L1 for the hardware to see this page table content */
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flush_cache_louis();
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return 0;
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}
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early_initcall(init_static_idmap);
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/*
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* In order to soft-boot, we need to switch to a 1:1 mapping for the
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* cpu_reset functions. This will then ensure that we have predictable
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* results when turning off the mmu.
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*/
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void setup_mm_for_reboot(void)
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{
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/* Switch to the identity mapping. */
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cpu_switch_mm(idmap_pgd, &init_mm);
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#ifdef CONFIG_CPU_HAS_ASID
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/*
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* We don't have a clean ASID for the identity mapping, which
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* may clash with virtual addresses of the previous page tables
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* and therefore potentially in the TLB.
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*/
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local_flush_tlb_all();
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#endif
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}
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