365bff806e
Until not so long ago, there were system log messages pointing to inconsistent MTRR setup of the video frame buffer caused by the way vesafb and X worked. While vesafb was fixed meanwhile, I believe fixing it there only hides a shortcoming in the MTRR code itself, in that that code is not symmetric with respect to the ordering of attempts to set up two (or more) regions where one contains the other. In the current shape, it permits only setting up sub-regions of pre-exisiting ones. The patch below makes this symmetric. While working on that I noticed a few more inconsistencies in that code, namely - use of 'unsigned int' for sizes in many, but not all places (the patch is converting this to use 'unsigned long' everywhere, which specifically might be necessary for x86-64 once a processor supporting more than 44 physical address bits would become available) - the code to correct inconsistent settings during secondary processor startup tried (if necessary) to correct, among other things, the value in IA32_MTRR_DEF_TYPE, however the newly computed value would never get used (i.e. stored in the respective MSR) - the generic range validation code checked that the end of the to-be-added range would be above 1MB; the value checked should have been the start of the range - when contained regions are detected, previously this was allowed only when the old region was uncacheable; this can be symmetric (i.e. the new region can also be uncacheable) and even further as per Intel's documentation write-trough and write-back for either region is also compatible with the respective opposite in the other Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de>
98 lines
2.5 KiB
C
98 lines
2.5 KiB
C
/*
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* local mtrr defines.
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*/
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#ifndef TRUE
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#define TRUE 1
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#define FALSE 0
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#endif
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#define MTRRcap_MSR 0x0fe
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#define MTRRdefType_MSR 0x2ff
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define NUM_FIXED_RANGES 88
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#define MTRRfix64K_00000_MSR 0x250
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#define MTRRfix16K_80000_MSR 0x258
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#define MTRRfix16K_A0000_MSR 0x259
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#define MTRRfix4K_C0000_MSR 0x268
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#define MTRRfix4K_C8000_MSR 0x269
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#define MTRRfix4K_D0000_MSR 0x26a
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#define MTRRfix4K_D8000_MSR 0x26b
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#define MTRRfix4K_E0000_MSR 0x26c
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#define MTRRfix4K_E8000_MSR 0x26d
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#define MTRRfix4K_F0000_MSR 0x26e
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#define MTRRfix4K_F8000_MSR 0x26f
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#define MTRR_CHANGE_MASK_FIXED 0x01
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#define MTRR_CHANGE_MASK_VARIABLE 0x02
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#define MTRR_CHANGE_MASK_DEFTYPE 0x04
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/* In the Intel processor's MTRR interface, the MTRR type is always held in
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an 8 bit field: */
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typedef u8 mtrr_type;
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struct mtrr_ops {
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u32 vendor;
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u32 use_intel_if;
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// void (*init)(void);
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void (*set)(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type);
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void (*set_all)(void);
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void (*get)(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type * type);
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int (*get_free_region)(unsigned long base, unsigned long size,
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int replace_reg);
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int (*validate_add_page)(unsigned long base, unsigned long size,
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unsigned int type);
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int (*have_wrcomb)(void);
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};
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extern int generic_get_free_region(unsigned long base, unsigned long size,
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int replace_reg);
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extern int generic_validate_add_page(unsigned long base, unsigned long size,
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unsigned int type);
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extern struct mtrr_ops generic_mtrr_ops;
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extern int positive_have_wrcomb(void);
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/* library functions for processor-specific routines */
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struct set_mtrr_context {
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unsigned long flags;
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unsigned long cr4val;
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u32 deftype_lo;
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u32 deftype_hi;
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u32 ccr3;
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};
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struct mtrr_var_range {
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u32 base_lo;
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u32 base_hi;
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u32 mask_lo;
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u32 mask_hi;
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};
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void set_mtrr_done(struct set_mtrr_context *ctxt);
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void set_mtrr_cache_disable(struct set_mtrr_context *ctxt);
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void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
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void get_mtrr_state(void);
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extern void set_mtrr_ops(struct mtrr_ops * ops);
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extern u32 size_or_mask, size_and_mask;
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extern struct mtrr_ops * mtrr_if;
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#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
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#define use_intel() (mtrr_if && mtrr_if->use_intel_if == 1)
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extern unsigned int num_var_ranges;
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void mtrr_state_warn(void);
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const char *mtrr_attrib_to_str(int x);
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void mtrr_wrmsr(unsigned, unsigned, unsigned);
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