417d6b9edb
Register the RTC resources for the sh775x subtype so that the new generic RTC support in drivers/rtc/rtc-sh.c will work. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
149 lines
3.5 KiB
C
149 lines
3.5 KiB
C
/*
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* SH7750/SH7751 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2006 Jamie Lenehan
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <asm/sci.h>
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffc80000,
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.end = 0xffc80000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Period IRQ */
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.start = 21,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* Carry IRQ */
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.start = 22,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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/* Alarm IRQ */
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 23, 24, 25, 0 },
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}, {
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.mapbase = 0xffe80000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 40, 41, 43, 42 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh7750_devices[] __initdata = {
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&rtc_device,
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&sci_device,
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};
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static int __init sh7750_devices_setup(void)
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{
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return platform_add_devices(sh7750_devices,
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ARRAY_SIZE(sh7750_devices));
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}
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__initcall(sh7750_devices_setup);
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static struct ipr_data sh7750_ipr_map[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 12, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 19, 0, 4, 2 }, /* TMU2 TIPCI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
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{ 21, 0, 0, 2 }, /* RTC PRI (period) */
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{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
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{ 23, 1, 4, 3 }, /* SCI ERI */
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{ 24, 1, 4, 3 }, /* SCI RXI */
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{ 25, 1, 4, 3 }, /* SCI TXI */
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{ 40, 2, 4, 3 }, /* SCIF ERI */
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{ 41, 2, 4, 3 }, /* SCIF RXI */
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{ 42, 2, 4, 3 }, /* SCIF BRI */
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{ 43, 2, 4, 3 }, /* SCIF TXI */
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{ 34, 2, 8, 7 }, /* DMAC DMTE0 */
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{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
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{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
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{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
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{ 28, 2, 8, 7 }, /* DMAC DMAE */
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};
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static struct ipr_data sh7751_ipr_map[] = {
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{ 44, 2, 8, 7 }, /* DMAC DMTE4 */
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{ 45, 2, 8, 7 }, /* DMAC DMTE5 */
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{ 46, 2, 8, 7 }, /* DMAC DMTE6 */
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{ 47, 2, 8, 7 }, /* DMAC DMTE7 */
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/* The following use INTC_INPRI00 for masking, which is a 32-bit
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register, not a 16-bit register like the IPRx registers, so it
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would need special support */
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/*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */
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/*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
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};
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static unsigned long ipr_offsets[] = {
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0xffd00004UL, /* 0: IPRA */
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0xffd00008UL, /* 1: IPRB */
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0xffd0000cUL, /* 2: IPRC */
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0xffd00010UL, /* 3: IPRD */
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};
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/* given the IPR index return the address of the IPR register */
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unsigned int map_ipridx_to_addr(int idx)
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{
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if (idx >= ARRAY_SIZE(ipr_offsets))
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return 0;
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return ipr_offsets[idx];
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}
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR_IRLM (1<<7)
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/* enable individual interrupt mode for external interupts */
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void ipr_irq_enable_irlm(void)
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{
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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}
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void __init init_IRQ_ipr()
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{
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make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map));
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#ifdef CONFIG_CPU_SUBTYPE_SH7751
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make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map));
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#endif
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}
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