kernel-fxtec-pro1x/include/asm-sh/cpu-sh4
Paul Mundt d04a0f79f5 sh: Fix up extended mode TLB for SH-X2+ cores.
The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot,
correspondingly, the PGD also has to be 64-bits, so fix that up.

The kernel and user permission bits really are decoupled in early
cuts of the silicon, which means that we also have to set corresponding
kernel permissions on user pages or we end up with user pages that the
kernel simply can't touch (!).

Finally, with those things corrected, really enable MMUCR.ME and
correct the PTEA value (this simply needs to be the upper 32-bits
of the PTE, with the size and protection bit encoding).

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2007-09-21 11:57:55 +09:00
..
addrspace.h
cache.h
cacheflush.h sh: Revert lazy dcache writeback changes. 2007-03-05 19:46:47 +09:00
dma-sh7780.h sh: dma: use __maybe_unused 2007-05-09 12:30:57 -07:00
dma.h sh: dma: use __maybe_unused 2007-05-09 12:30:57 -07:00
freq.h sh: remove support for sh73180 and solution engine 73180 2007-07-25 10:49:21 +09:00
mmu_context.h sh: Fix up extended mode TLB for SH-X2+ cores. 2007-09-21 11:57:55 +09:00
sigcontext.h
sq.h
timer.h sh: Preliminary support for the SH-X3 CPU. 2007-06-20 18:27:10 +09:00
ubc.h
watchdog.h