148 lines
3.4 KiB
C
148 lines
3.4 KiB
C
#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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struct pci_dn;
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enum pnv_phb_type {
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PNV_PHB_P5IOC2,
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PNV_PHB_IODA1,
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PNV_PHB_IODA2,
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};
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/* Precise PHB model for error management */
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enum pnv_phb_model {
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PNV_PHB_MODEL_UNKNOWN,
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PNV_PHB_MODEL_P5IOC2,
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PNV_PHB_MODEL_P7IOC,
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};
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#define PNV_PCI_DIAG_BUF_SIZE 4096
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/* Data associated with a PE, including IOMMU tracking etc.. */
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struct pnv_ioda_pe {
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/* A PE can be associated with a single device or an
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* entire bus (& children). In the former case, pdev
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* is populated, in the later case, pbus is.
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*/
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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/* Effective RID (device RID for a device PE and base bus
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* RID with devfn 0 for a bus PE)
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*/
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unsigned int rid;
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/* PE number */
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unsigned int pe_number;
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/* "Weight" assigned to the PE for the sake of DMA resource
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* allocations
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*/
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unsigned int dma_weight;
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/* This is a PCI-E -> PCI-X bridge, this points to the
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* corresponding bus PE
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*/
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struct pnv_ioda_pe *bus_pe;
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/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
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int tce32_seg;
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int tce32_segcount;
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struct iommu_table tce32_table;
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/* XXX TODO: Add support for additional 64-bit iommus */
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/* MSIs. MVE index is identical for for 32 and 64 bit MSI
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* and -1 if not supported. (It's actually identical to the
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* PE number)
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*/
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int mve_number;
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/* Link in list of PE#s */
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struct list_head link;
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};
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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enum pnv_phb_model model;
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u64 opal_id;
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void __iomem *regs;
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spinlock_t lock;
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#ifdef CONFIG_PCI_MSI
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unsigned long *msi_map;
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unsigned int msi_base;
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unsigned int msi_count;
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unsigned int msi_next;
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unsigned int msi32_support;
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#endif
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int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int is_64,
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struct msi_msg *msg);
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void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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void (*fixup_phb)(struct pci_controller *hose);
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u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
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union {
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struct {
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struct iommu_table iommu_table;
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} p5ioc2;
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struct {
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/* Global bridge info */
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unsigned int total_pe;
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unsigned int m32_size;
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unsigned int m32_segsize;
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unsigned int m32_pci_base;
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unsigned int io_size;
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unsigned int io_segsize;
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unsigned int io_pci_base;
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/* PE allocation bitmap */
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unsigned long *pe_alloc;
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/* M32 & IO segment maps */
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unsigned int *m32_segmap;
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unsigned int *io_segmap;
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struct pnv_ioda_pe *pe_array;
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/* Reverse map of PEs, will have to extend if
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* we are to support more than 256 PEs, indexed
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* bus { bus, devfn }
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*/
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unsigned char pe_rmap[0x10000];
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/* 32-bit TCE tables allocation */
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unsigned long tce32_count;
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/* Total "weight" for the sake of DMA resources
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* allocation
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*/
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unsigned int dma_weight;
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unsigned int dma_pe_count;
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/* Sorted list of used PE's, sorted at
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* boot for resource allocation purposes
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*/
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struct list_head pe_list;
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} ioda;
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};
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/* PHB status structure */
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union {
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unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
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struct OpalIoP7IOCPhbErrorData p7ioc;
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} diag;
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};
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extern struct pci_ops pnv_pci_ops;
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extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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u64 dma_offset);
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extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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#endif /* __POWERNV_PCI_H */
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