8e4b97e3b8
This patch adds the missing gpi28 to the supported GPIOs in the GPI P3 "chip". Signed-off-by: Roland Stigge <stigge@antcom.de>
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
/*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_GPIO_LPC32XX_H
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#define __MACH_GPIO_LPC32XX_H
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/*
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* Note!
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* Muxed GP pins need to be setup to the GP state in the board level
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* code prior to using this driver.
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* GPI pins : 28xP3 group
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* GPO pins : 24xP3 group
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* GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
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*/
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#define LPC32XX_GPIO_P0_MAX 8
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#define LPC32XX_GPIO_P1_MAX 24
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#define LPC32XX_GPIO_P2_MAX 13
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#define LPC32XX_GPIO_P3_MAX 6
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#define LPC32XX_GPI_P3_MAX 29
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#define LPC32XX_GPO_P3_MAX 24
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#define LPC32XX_GPIO_P0_GRP 0
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#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
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#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
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#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
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#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
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#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
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/*
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* A specific GPIO can be selected with this macro
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* ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
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* See the LPC32x0 User's guide for GPIO group numbers
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*/
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#define LPC32XX_GPIO(x, y) ((x) + (y))
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#endif /* __MACH_GPIO_LPC32XX_H */
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