d6473f5664
Introduced a new vm specfic callback insert_page() to program a single pte in ggtt or ppgtt. This allows us to map a single page in to the mappable aperture space. This can be iterated over to access the whole object by using space as meagre as page size. v2: Added low level rpm assertions to insert_page routines (Chris) v3: Added POSTING_READ post register write (Tvrtko) v4: Rebase (Ankit) v5: Removed wmb() and FLUSH_CTL from insert_page, caller to take care of it (Chris) v6: insert_page not working correctly without FLSH_CNTL write, added the write again. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
35 lines
941 B
C
35 lines
941 B
C
/* Common header for intel-gtt.ko and i915.ko */
|
|
|
|
#ifndef _DRM_INTEL_GTT_H
|
|
#define _DRM_INTEL_GTT_H
|
|
|
|
void intel_gtt_get(u64 *gtt_total, size_t *stolen_size,
|
|
phys_addr_t *mappable_base, u64 *mappable_end);
|
|
|
|
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
|
|
struct agp_bridge_data *bridge);
|
|
void intel_gmch_remove(void);
|
|
|
|
bool intel_enable_gtt(void);
|
|
|
|
void intel_gtt_chipset_flush(void);
|
|
void intel_gtt_insert_page(dma_addr_t addr,
|
|
unsigned int pg,
|
|
unsigned int flags);
|
|
void intel_gtt_insert_sg_entries(struct sg_table *st,
|
|
unsigned int pg_start,
|
|
unsigned int flags);
|
|
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
|
|
|
|
/* Special gtt memory types */
|
|
#define AGP_DCACHE_MEMORY 1
|
|
#define AGP_PHYS_MEMORY 2
|
|
|
|
/* flag for GFDT type */
|
|
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
extern int intel_iommu_gfx_mapped;
|
|
#endif
|
|
|
|
#endif
|