e6982c671c
This patch adds __cpuinit and __cpuinitdata sections that need to exist past boot to support cpu hotplug. Caveat: This is done *only* for EM64T CPU Hotplug support, on request from Andi Kleen. Much of the generic hotplug code in kernel, and none of the other archs that support CPU hotplug today, i386, ia64, ppc64, s390 and parisc dont mark sections with __cpuinit, but only mark them as __devinit, and __devinitdata. If someone is motivated to change generic code, we need to make sure all existing hotplug code does not break, on other arch's that dont use __cpuinit, and __cpudevinit. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Acked-by: Andi Kleen <ak@muc.de> Acked-by: Zwane Mwaikambo <zwane@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/*
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* Intel specific MCE features.
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* Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/mce.h>
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#include <asm/hw_irq.h>
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static DEFINE_PER_CPU(unsigned long, next_check);
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asmlinkage void smp_thermal_interrupt(void)
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{
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struct mce m;
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ack_APIC_irq();
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irq_enter();
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if (time_before(jiffies, __get_cpu_var(next_check)))
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goto done;
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__get_cpu_var(next_check) = jiffies + HZ*300;
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memset(&m, 0, sizeof(m));
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m.cpu = smp_processor_id();
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m.bank = MCE_THERMAL_BANK;
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rdtscll(m.tsc);
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rdmsrl(MSR_IA32_THERM_STATUS, m.status);
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if (m.status & 0x1) {
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printk(KERN_EMERG
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"CPU%d: Temperature above threshold, cpu clock throttled\n", m.cpu);
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add_taint(TAINT_MACHINE_CHECK);
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} else {
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printk(KERN_EMERG "CPU%d: Temperature/speed normal\n", m.cpu);
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}
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mce_log(&m);
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done:
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irq_exit();
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}
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static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int tm2 = 0;
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unsigned int cpu = smp_processor_id();
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if (!cpu_has(c, X86_FEATURE_ACPI))
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return;
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if (!cpu_has(c, X86_FEATURE_ACC))
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return;
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/* first check if TM1 is already enabled by the BIOS, in which
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* case there might be some SMM goo which handles it, so we can't even
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* put a handler since it might be delivered via SMI already.
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*/
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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h = apic_read(APIC_LVTTHMR);
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if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {
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printk(KERN_DEBUG
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"CPU%d: Thermal monitoring handled by SMI\n", cpu);
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return;
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}
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if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))
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tm2 = 1;
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if (h & APIC_VECTOR_MASK) {
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printk(KERN_DEBUG
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"CPU%d: Thermal LVT vector (%#x) already "
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"installed\n", cpu, (h & APIC_VECTOR_MASK));
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return;
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}
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h = THERMAL_APIC_VECTOR;
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h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
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apic_write_around(APIC_LVTTHMR, h);
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rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
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wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
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l = apic_read(APIC_LVTTHMR);
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apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
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cpu, tm2 ? "TM2" : "TM1");
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return;
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}
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void __cpuinit mce_intel_feature_init(struct cpuinfo_x86 *c)
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{
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intel_init_thermal(c);
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}
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