ad611045ce
The PCI bridge on the Holly board is incorrectly represented in the device tree. The current device tree node for the PCI bridge sits under the tsi-bridge node. That's not obviously wrong, but the PCI bridge translates some PCI spaces into CPU address ranges which were not translated by the "ranges" property in tsi-bridge node. We used to get away with this problem because the PCI bridge discovery code was also buggy, assuming incorrectly that PCI host bridge nodes were always directly under the root bus and treating the translated addresses as raw CPU addresses, rather than parent bus addresses. This has since been fixed, thus breaking Holly. This could be fixed by adding extra translations to the tsi-bridge node, but this patch instead moves the Holly PCI bridge out of the tsi-bridge node to the root bus. This makes the tsi-bridge node represent only the built-in IO devices in the bridge, with a more-or-less contiguous address range. This is the same convention used on Freescale SoC chips, where the "soc" node represents only the IMMR region, and the PCI and other bus bridges are separate nodes under the root bus. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
197 lines
4.8 KiB
Text
197 lines
4.8 KiB
Text
/*
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* Device Tree Source for IBM Holly (PPC 750CL with TSI controller)
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* Copyright 2007, IBM Corporation
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*
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* Stephen Winiecki <stevewin@us.ibm.com>
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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model = "41K7339";
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compatible = "ibm,holly";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells =<0>;
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PowerPC,750CL@0 {
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device_type = "cpu";
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reg = <0x00000000>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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d-cache-sets = <128>;
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i-cache-sets = <128>;
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timebase-frequency = <50000000>;
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clock-frequency = <600000000>;
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bus-frequency = <200000000>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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tsi109@c0000000 {
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device_type = "tsi-bridge";
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compatible = "tsi109-bridge", "tsi108-bridge";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xc0000000 0x00010000>;
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reg = <0xc0000000 0x00010000>;
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i2c@7000 {
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device_type = "i2c";
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compatible = "tsi109-i2c", "tsi108-i2c";
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interrupt-parent = <&MPIC>;
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interrupts = <0xe 0x2>;
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reg = <0x00007000 0x00000400>;
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};
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MDIO: mdio@6000 {
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device_type = "mdio";
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compatible = "tsi109-mdio", "tsi108-mdio";
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reg = <0x00006000 0x00000050>;
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#address-cells = <1>;
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#size-cells = <0>;
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PHY1: ethernet-phy@1 {
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compatible = "bcm5461a";
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reg = <0x00000001>;
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txc-rxc-delay-disable;
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};
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PHY2: ethernet-phy@2 {
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compatible = "bcm5461a";
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reg = <0x00000002>;
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txc-rxc-delay-disable;
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};
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};
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ethernet@6200 {
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device_type = "network";
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compatible = "tsi109-ethernet", "tsi108-ethernet";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00006000 0x00000200>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupt-parent = <&MPIC>;
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interrupts = <0x10 0x2>;
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mdio-handle = <&MDIO>;
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phy-handle = <&PHY1>;
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};
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ethernet@6600 {
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device_type = "network";
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compatible = "tsi109-ethernet", "tsi108-ethernet";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00006400 0x00000200>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupt-parent = <&MPIC>;
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interrupts = <0x11 0x2>;
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mdio-handle = <&MDIO>;
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phy-handle = <&PHY2>;
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};
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serial@7808 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x00007808 0x00000200>;
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virtual-reg = <0xc0007808>;
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clock-frequency = <1067212800>;
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current-speed = <115200>;
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interrupt-parent = <&MPIC>;
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interrupts = <0xc 0x2>;
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};
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serial@7c08 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x00007c08 0x00000200>;
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virtual-reg = <0xc0007c08>;
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clock-frequency = <1067212800>;
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current-speed = <115200>;
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interrupt-parent = <&MPIC>;
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interrupts = <0xd 0x2>;
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};
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MPIC: pic@7400 {
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device_type = "open-pic";
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compatible = "chrp,open-pic";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x00007400 0x00000400>;
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big-endian;
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};
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};
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pci@c0001000 {
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device_type = "pci";
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compatible = "tsi109-pci", "tsi108-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xc0001000 0x00001000>;
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bus-range = <0x0 0x0>;
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/*----------------------------------------------------+
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| PCI memory range.
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| 01 denotes I/O space
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| 02 denotes 32-bit memory space
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+----------------------------------------------------*/
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ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000
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0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>;
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clock-frequency = <133333332>;
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interrupt-parent = <&MPIC>;
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interrupts = <0x17 0x2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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/*----------------------------------------------------+
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| The INTA, INTB, INTC, INTD are shared.
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+----------------------------------------------------*/
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interrupt-map = <
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0x800 0x0 0x0 0x1 &RT0 0x24 0x0
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0x800 0x0 0x0 0x2 &RT0 0x25 0x0
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0x800 0x0 0x0 0x3 &RT0 0x26 0x0
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0x800 0x0 0x0 0x4 &RT0 0x27 0x0
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0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
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0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
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0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
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0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
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0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
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0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
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0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
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0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
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0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
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0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
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0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
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0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
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>;
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RT0: router@1180 {
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device_type = "pic-router";
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interrupt-controller;
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big-endian;
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clock-frequency = <0>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x17 0x2>;
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interrupt-parent = <&MPIC>;
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};
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};
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chosen {
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linux,stdout-path = "/tsi109@c0000000/serial@7808";
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};
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};
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