6845664a6a
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
142 lines
3.7 KiB
C
142 lines
3.7 KiB
C
/* arch/arm/plat-samsung/irq-uart.c
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* originally part of arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Samsung- UART Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/irq-uart.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
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{
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struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
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return uirq->regs;
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}
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static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
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{
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return irq & 3;
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}
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static void s3c_irq_uart_mask(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_maskack(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_uart_unmask(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg &= ~(1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_ack(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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{
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struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
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u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
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int base = uirq->base_irq;
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if (pend & (1 << 0))
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generic_handle_irq(base);
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if (pend & (1 << 1))
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generic_handle_irq(base + 1);
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if (pend & (1 << 2))
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generic_handle_irq(base + 2);
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if (pend & (1 << 3))
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generic_handle_irq(base + 3);
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}
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static struct irq_chip s3c_irq_uart = {
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.name = "s3c-uart",
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.irq_mask = s3c_irq_uart_mask,
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.irq_unmask = s3c_irq_uart_unmask,
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.irq_mask_ack = s3c_irq_uart_maskack,
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.irq_ack = s3c_irq_uart_ack,
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};
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static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
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{
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void __iomem *reg_base = uirq->regs;
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unsigned int irq;
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int offs;
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/* mask all interrupts at the start. */
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__raw_writel(0xf, reg_base + S3C64XX_UINTM);
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for (offs = 0; offs < 3; offs++) {
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irq = uirq->base_irq + offs;
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irq_set_chip(irq, &s3c_irq_uart);
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irq_set_chip_data(irq, uirq);
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irq_set_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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irq_set_handler_data(uirq->parent_irq, uirq);
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irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
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}
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/**
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* s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
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* @irq: The interrupt data for registering
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* @nr_irqs: The number of interrupt descriptions in @irq.
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*
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* Register the UART interrupts specified by @irq including the demuxing
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* routines. This supports the S3C6400 and newer style of devices.
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*/
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void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
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{
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for (; nr_irqs > 0; nr_irqs--, irq++)
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s3c_init_uart_irq(irq);
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}
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