efc1bb8a6f
This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
224 lines
5.4 KiB
ArmAsm
224 lines
5.4 KiB
ArmAsm
/*
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* (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* replicated define because linux/bitops.h cannot be included in assembly */
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#define BIT(nr) (1 << (nr))
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/psc.h>
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#include <mach/memory.h>
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#include "clock.h"
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/* Arbitrary, hardware currently does not update PHYRDY correctly */
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#define PHYRDY_CYCLES 0x1000
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/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
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#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
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#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
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#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
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#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
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.text
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/*
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* Move DaVinci into deep sleep state
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*
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* Note: This code is copied to internal SRAM by PM code. When the DaVinci
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* wakes up it continues execution at the point it went to sleep.
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* Register Usage:
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* r0: contains virtual base for DDR2 controller
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* r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
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* r2: contains PSC number for DDR2
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* r3: contains virtual base DDR2 PLL controller
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* r4: contains virtual address of the DEEPSLEEP register
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*/
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ENTRY(davinci_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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ldr ip, CACHE_FLUSH
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blx ip
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ldmia r0, {r0-r4}
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/*
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* Switch DDR to self-refresh mode.
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*/
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/* calculate SDRCR address */
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_SRPD_BIT
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orr ip, ip, #DDR2_LPMODEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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orr ip, ip, #DDR2_MCLKSTOPEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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mov ip, #PHYRDY_CYCLES
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1: subs ip, ip, #0x1
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bne 1b
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/* Disable DDR2 LPSC */
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mov r7, r0
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mov r0, #0x2
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bl davinci_ddr_psc_config
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mov r0, r7
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/* Disable clock to DDR PHY */
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ldr ip, [r3, #PLLDIV1]
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bic ip, ip, #PLLDIV_EN
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str ip, [r3, #PLLDIV1]
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/* Put the DDR PLL in bypass and power down */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLENSRC
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bic ip, ip, #PLLCTL_PLLEN
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str ip, [r3, #PLLCTL]
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/* Wait for PLL to switch to bypass */
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mov ip, #PLL_BYPASS_CYCLES
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2: subs ip, ip, #0x1
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bne 2b
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/* Power down the PLL */
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ldr ip, [r3, #PLLCTL]
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orr ip, ip, #PLLCTL_PLLPWRDN
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str ip, [r3, #PLLCTL]
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/* Go to deep sleep */
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ldr ip, [r4]
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orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
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/* System goes to sleep beyond after this instruction */
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str ip, [r4]
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/* Wake up from sleep */
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/* Clear sleep enable */
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ldr ip, [r4]
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bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
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str ip, [r4]
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/* initialize the DDR PLL controller */
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/* Put PLL in reset */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLRST
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str ip, [r3, #PLLCTL]
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/* Clear PLL power down */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLPWRDN
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str ip, [r3, #PLLCTL]
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mov ip, #PLL_RESET_CYCLES
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3: subs ip, ip, #0x1
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bne 3b
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/* Bring PLL out of reset */
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ldr ip, [r3, #PLLCTL]
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orr ip, ip, #PLLCTL_PLLRST
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str ip, [r3, #PLLCTL]
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/* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
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mov ip, #PLL_LOCK_CYCLES
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4: subs ip, ip, #0x1
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bne 4b
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/* Remove PLL from bypass mode */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLENSRC
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orr ip, ip, #PLLCTL_PLLEN
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str ip, [r3, #PLLCTL]
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/* Start 2x clock to DDR2 */
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ldr ip, [r3, #PLLDIV1]
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orr ip, ip, #PLLDIV_EN
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str ip, [r3, #PLLDIV1]
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/* Enable VCLK */
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/* Enable DDR2 LPSC */
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mov r7, r0
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mov r0, #0x3
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bl davinci_ddr_psc_config
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mov r0, r7
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/* clear MCLKSTOPEN */
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_MCLKSTOPEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_LPMODEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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/* Restore registers and return */
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ldmfd sp!, {r0-r12, pc}
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ENDPROC(davinci_cpu_suspend)
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/*
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* Disables or Enables DDR2 LPSC
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* Register Usage:
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* r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
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* r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
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* r2: contains PSC number for DDR2
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*/
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ENTRY(davinci_ddr_psc_config)
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/* Set next state in mdctl for DDR2 */
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mov r6, #MDCTL
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add r6, r6, r2, lsl #2
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ldr ip, [r1, r6]
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bic ip, ip, #MDSTAT_STATE_MASK
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orr ip, ip, r0
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str ip, [r1, r6]
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/* Enable the Power Domain Transition Command */
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ldr ip, [r1, #PTCMD]
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orr ip, ip, #0x1
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str ip, [r1, #PTCMD]
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/* Check for Transition Complete (PTSTAT) */
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ptstat_done:
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ldr ip, [r1, #PTSTAT]
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and ip, ip, #0x1
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cmp ip, #0x0
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bne ptstat_done
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/* Check for DDR2 clock disable completion; */
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mov r6, #MDSTAT
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add r6, r6, r2, lsl #2
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ddr2clk_stop_done:
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ldr ip, [r1, r6]
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and ip, ip, #MDSTAT_STATE_MASK
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cmp ip, r0
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bne ddr2clk_stop_done
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mov pc, lr
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ENDPROC(davinci_ddr_psc_config)
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CACHE_FLUSH:
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.word arm926_flush_kern_cache_all
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ENTRY(davinci_cpu_suspend_sz)
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.word . - davinci_cpu_suspend
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ENDPROC(davinci_cpu_suspend_sz)
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