1c9d3df5e8
If PG_dcache_dirty is set for a page, we need to flush the source page before performing any copypage operation using a different virtual address. This fixes the copypage implementations for XScale, StrongARM and ARMv6. This patch fixes segmentation faults seen in the dynamic linker under the usage patterns in glibc 2.4/2.5. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/*
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* linux/arch/arm/lib/copypage-xscale.S
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*
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* Copyright (C) 1995-2005 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This handles the mini data cache, as found on SA11x0 and XScale
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* processors. When we copy a user page page, we map it in such a way
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* that accesses to this page will not touch the main data cache, but
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* will be cached in the mini data cache. This prevents us thrashing
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* the main data cache on page faults.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include "mm.h"
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/*
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* 0xffff8000 to 0xffffffff is reserved for any ARM architecture
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* specific hacks for copying pages efficiently.
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*/
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#define COPYPAGE_MINICACHE 0xffff8000
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#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
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L_PTE_CACHEABLE)
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static DEFINE_SPINLOCK(minicache_lock);
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/*
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* XScale mini-dcache optimised copy_user_page
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*
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* We flush the destination cache lines just before we write the data into the
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* corresponding address. Since the Dcache is read-allocate, this removes the
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* Dcache aliasing issue. The writes will be forwarded to the write buffer,
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* and merged as appropriate.
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*/
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static void __attribute__((naked))
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mc_copy_user_page(void *from, void *to)
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{
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/*
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* Strangely enough, best performance is achieved
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* when prefetching destination as well. (NP)
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*/
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asm volatile(
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"stmfd sp!, {r4, r5, lr} \n\
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mov lr, %2 \n\
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pld [r0, #0] \n\
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pld [r0, #32] \n\
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pld [r1, #0] \n\
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pld [r1, #32] \n\
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1: pld [r0, #64] \n\
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pld [r0, #96] \n\
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pld [r1, #64] \n\
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pld [r1, #96] \n\
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2: ldrd r2, [r0], #8 \n\
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ldrd r4, [r0], #8 \n\
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mov ip, r1 \n\
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strd r2, [r1], #8 \n\
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ldrd r2, [r0], #8 \n\
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strd r4, [r1], #8 \n\
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ldrd r4, [r0], #8 \n\
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strd r2, [r1], #8 \n\
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strd r4, [r1], #8 \n\
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mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
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ldrd r2, [r0], #8 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
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ldrd r4, [r0], #8 \n\
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mov ip, r1 \n\
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strd r2, [r1], #8 \n\
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ldrd r2, [r0], #8 \n\
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strd r4, [r1], #8 \n\
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ldrd r4, [r0], #8 \n\
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strd r2, [r1], #8 \n\
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strd r4, [r1], #8 \n\
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mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
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subs lr, lr, #1 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
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bgt 1b \n\
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beq 2b \n\
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ldmfd sp!, {r4, r5, pc} "
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:
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: "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
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}
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void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
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{
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struct page *page = virt_to_page(kfrom);
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if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
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__flush_dcache_page(page_mapping(page), page);
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spin_lock(&minicache_lock);
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set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
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flush_tlb_kernel_page(COPYPAGE_MINICACHE);
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mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
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spin_unlock(&minicache_lock);
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}
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/*
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* XScale optimised clear_user_page
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*/
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void __attribute__((naked))
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xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr)
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{
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asm volatile(
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"mov r1, %0 \n\
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mov r2, #0 \n\
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mov r3, #0 \n\
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1: mov ip, r0 \n\
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strd r2, [r0], #8 \n\
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strd r2, [r0], #8 \n\
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strd r2, [r0], #8 \n\
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strd r2, [r0], #8 \n\
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mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
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subs r1, r1, #1 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
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bne 1b \n\
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mov pc, lr"
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:
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: "I" (PAGE_SIZE / 32));
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}
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struct cpu_user_fns xscale_mc_user_fns __initdata = {
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.cpu_clear_user_page = xscale_mc_clear_user_page,
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.cpu_copy_user_page = xscale_mc_copy_user_page,
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};
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