a6dc77254b
Pull ARM DMA engine updates from Russell King: "This looks scary at first glance, but what it is is: - a rework of the sa11x0 DMA engine driver merged during the previous cycle, to extract a common set of helper functions for DMA engine implementations. - conversion of amba-pl08x.c to use these helper functions. - addition of OMAP DMA engine driver (using these helper functions), and conversion of some of the OMAP DMA users to use DMA engine. Nothing in the helper functions is ARM specific, so I hope that other implementations can consolidate some of their code by making use of these helpers. This has been sitting in linux-next most of the merge cycle, and has been tested by several OMAP folk. I've tested it on sa11x0 platforms, and given it my best shot on my broken platforms which have the amba-pl08x controller. The last point is the addition to feature-removal-schedule.txt, which will have a merge conflict. Between myself and TI, we're planning to remove the old TI DMA implementation next year." Fix up trivial add/add conflicts in Documentation/feature-removal-schedule.txt and drivers/dma/{Kconfig,Makefile} * 'dmaengine' of git://git.linaro.org/people/rmk/linux-arm: (53 commits) ARM: 7481/1: OMAP2+: omap2plus_defconfig: enable OMAP DMA engine ARM: 7464/1: mmc: omap_hsmmc: ensure probe returns error if DMA channel request fails Add feature removal of old OMAP private DMA implementation mtd: omap2: remove private DMA API implementation mtd: omap2: add DMA engine support spi: omap2-mcspi: remove private DMA API implementation spi: omap2-mcspi: add DMA engine support ARM: omap: remove mmc platform data dma_mask and initialization mmc: omap: remove private DMA API implementation mmc: omap: add DMA engine support mmc: omap_hsmmc: remove private DMA API implementation mmc: omap_hsmmc: add DMA engine support dmaengine: omap: add support for cyclic DMA dmaengine: omap: add support for setting fi dmaengine: omap: add support for returning residue in tx_state method dmaengine: add OMAP DMA engine driver dmaengine: sa11x0-dma: add cyclic DMA support dmaengine: sa11x0-dma: fix DMA residue support dmaengine: PL08x: ensure all descriptors are freed when channel is released dmaengine: PL08x: get rid of write only pool_ctr and free_txd locking ...
446 lines
9.1 KiB
C
446 lines
9.1 KiB
C
/*
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* arch/arm/mach-spear6xx/spear6xx.c
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*
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* SPEAr6XX machines common source file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Rajeev Kumar<rajeev-dlh.kumar@st.com>
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*
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* Copyright 2012 Stefan Roese <sr@denx.de>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/amba/pl08x.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/pl080.h>
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#include <asm/hardware/vic.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <plat/pl080.h>
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#include <mach/generic.h>
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#include <mach/spear.h>
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/* dmac device registration */
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static struct pl08x_channel_data spear600_dma_info[] = {
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{
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.bus_id = "ssp1_rx",
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.min_signal = 0,
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.max_signal = 0,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp1_tx",
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.min_signal = 1,
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.max_signal = 1,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart0_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart0_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart1_rx",
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.min_signal = 4,
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.max_signal = 4,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart1_tx",
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.min_signal = 5,
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.max_signal = 5,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp2_rx",
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.min_signal = 6,
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.max_signal = 6,
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.muxval = 0,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ssp2_tx",
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.min_signal = 7,
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.max_signal = 7,
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.muxval = 0,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ssp0_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "irda",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "adc",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 0,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "to_jpeg",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "from_jpeg",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras0_rx",
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.min_signal = 0,
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.max_signal = 0,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras0_tx",
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.min_signal = 1,
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.max_signal = 1,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras1_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras1_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras2_rx",
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.min_signal = 4,
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.max_signal = 4,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras2_tx",
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.min_signal = 5,
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.max_signal = 5,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras3_rx",
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.min_signal = 6,
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.max_signal = 6,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras3_tx",
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.min_signal = 7,
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.max_signal = 7,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras4_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras4_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras5_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras5_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras6_rx",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras6_tx",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras7_rx",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras7_tx",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ext0_rx",
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.min_signal = 0,
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.max_signal = 0,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext0_tx",
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.min_signal = 1,
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.max_signal = 1,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext1_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext1_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext2_rx",
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.min_signal = 4,
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.max_signal = 4,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext2_tx",
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.min_signal = 5,
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.max_signal = 5,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext3_rx",
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.min_signal = 6,
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.max_signal = 6,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext3_tx",
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.min_signal = 7,
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.max_signal = 7,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext4_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext4_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext5_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext5_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext6_rx",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext6_tx",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext7_rx",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ext7_tx",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 2,
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.periph_buses = PL08X_AHB2,
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},
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};
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struct pl08x_platform_data pl080_plat_data = {
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.memcpy_channel = {
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.bus_id = "memcpy",
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.cctl_memcpy =
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(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
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PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
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PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
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PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
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PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
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PL080_CONTROL_PROT_SYS),
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},
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.lli_buses = PL08X_AHB1,
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.mem_buses = PL08X_AHB1,
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.get_signal = pl080_get_signal,
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.put_signal = pl080_put_signal,
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.slave_channels = spear600_dma_info,
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.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
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};
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/*
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* Following will create 16MB static virtual/physical mappings
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* PHYSICAL VIRTUAL
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* 0xF0000000 0xF0000000
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* 0xF1000000 0xF1000000
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* 0xD0000000 0xFD000000
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* 0xFC000000 0xFC000000
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*/
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struct map_desc spear6xx_io_desc[] __initdata = {
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{
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.virtual = VA_SPEAR6XX_ML_CPU_BASE,
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.pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
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.length = 2 * SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = VA_SPEAR6XX_ICM1_BASE,
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.pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
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.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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},
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};
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/* This will create static memory mapping for selected devices */
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void __init spear6xx_map_io(void)
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{
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iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
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}
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static void __init spear6xx_timer_init(void)
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{
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char pclk_name[] = "pll3_clk";
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struct clk *gpt_clk, *pclk;
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spear6xx_clk_init();
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/* get the system timer clock */
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gpt_clk = clk_get_sys("gpt0", NULL);
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if (IS_ERR(gpt_clk)) {
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pr_err("%s:couldn't get clk for gpt\n", __func__);
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BUG();
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}
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/* get the suitable parent clock for timer*/
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pclk = clk_get(NULL, pclk_name);
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if (IS_ERR(pclk)) {
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pr_err("%s:couldn't get %s as parent for gpt\n",
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__func__, pclk_name);
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BUG();
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}
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clk_set_parent(gpt_clk, pclk);
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clk_put(gpt_clk);
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clk_put(pclk);
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spear_setup_of_timer();
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}
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struct sys_timer spear6xx_timer = {
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.init = spear6xx_timer_init,
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};
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/* Add auxdata to pass platform data */
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struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
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&pl080_plat_data),
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{}
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};
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static void __init spear600_dt_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table,
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spear6xx_auxdata_lookup, NULL);
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}
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static const char *spear600_dt_board_compat[] = {
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"st,spear600",
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NULL
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};
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static const struct of_device_id vic_of_match[] __initconst = {
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{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
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{ /* Sentinel */ }
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};
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static void __init spear6xx_dt_init_irq(void)
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{
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of_irq_init(vic_of_match);
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}
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DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
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.map_io = spear6xx_map_io,
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.init_irq = spear6xx_dt_init_irq,
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.handle_irq = vic_handle_irq,
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.timer = &spear6xx_timer,
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.init_machine = spear600_dt_init,
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.restart = spear_restart,
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.dt_compat = spear600_dt_board_compat,
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MACHINE_END
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