6a2df3a872
The system call path in entry[64].S is run with interrupts enabled. Remove the irq tracing check from the system call exit code. If a program check interrupted a context enabled for interrupts do a call to trace_irq_off_caller in the program check handler before branching to the system call exit code. Restructure the system call and io interrupt return code to avoid avoid the lpsw[e] to disable machine checks. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
478 lines
11 KiB
C
478 lines
11 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#include <asm/setup.h>
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#include <asm/processor.h>
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#include <asm/lowcore.h>
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#ifdef __KERNEL__
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struct task_struct;
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extern struct task_struct *__switch_to(void *, void *);
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static inline void save_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile(
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" std 0,%O0+8(%R0)\n"
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" std 2,%O0+24(%R0)\n"
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" std 4,%O0+40(%R0)\n"
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" std 6,%O0+56(%R0)"
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: "=Q" (*fpregs) : "Q" (*fpregs));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" stfpc %0\n"
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" std 1,%O0+16(%R0)\n"
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" std 3,%O0+32(%R0)\n"
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" std 5,%O0+48(%R0)\n"
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" std 7,%O0+64(%R0)\n"
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" std 8,%O0+72(%R0)\n"
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" std 9,%O0+80(%R0)\n"
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" std 10,%O0+88(%R0)\n"
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" std 11,%O0+96(%R0)\n"
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" std 12,%O0+104(%R0)\n"
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" std 13,%O0+112(%R0)\n"
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" std 14,%O0+120(%R0)\n"
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" std 15,%O0+128(%R0)\n"
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: "=Q" (*fpregs) : "Q" (*fpregs));
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}
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static inline void restore_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile(
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" ld 0,%O0+8(%R0)\n"
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" ld 2,%O0+24(%R0)\n"
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" ld 4,%O0+40(%R0)\n"
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" ld 6,%O0+56(%R0)"
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: : "Q" (*fpregs));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" lfpc %0\n"
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" ld 1,%O0+16(%R0)\n"
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" ld 3,%O0+32(%R0)\n"
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" ld 5,%O0+48(%R0)\n"
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" ld 7,%O0+64(%R0)\n"
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" ld 8,%O0+72(%R0)\n"
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" ld 9,%O0+80(%R0)\n"
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" ld 10,%O0+88(%R0)\n"
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" ld 11,%O0+96(%R0)\n"
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" ld 12,%O0+104(%R0)\n"
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" ld 13,%O0+112(%R0)\n"
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" ld 14,%O0+120(%R0)\n"
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" ld 15,%O0+128(%R0)\n"
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: : "Q" (*fpregs));
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}
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static inline void save_access_regs(unsigned int *acrs)
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{
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asm volatile("stam 0,15,%0" : "=Q" (*acrs));
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}
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static inline void restore_access_regs(unsigned int *acrs)
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{
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asm volatile("lam 0,15,%0" : : "Q" (*acrs));
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}
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#define switch_to(prev,next,last) do { \
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if (prev == next) \
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break; \
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save_fp_regs(&prev->thread.fp_regs); \
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restore_fp_regs(&next->thread.fp_regs); \
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save_access_regs(&prev->thread.acrs[0]); \
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restore_access_regs(&next->thread.acrs[0]); \
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prev = __switch_to(prev,next); \
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} while (0)
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extern void account_vtime(struct task_struct *, struct task_struct *);
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extern void account_tick_vtime(struct task_struct *);
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extern void account_system_vtime(struct task_struct *);
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#ifdef CONFIG_PFAULT
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extern void pfault_irq_init(void);
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extern int pfault_init(void);
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extern void pfault_fini(void);
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#else /* CONFIG_PFAULT */
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#define pfault_irq_init() do { } while (0)
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#define pfault_init() ({-1;})
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#define pfault_fini() do { } while (0)
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#endif /* CONFIG_PFAULT */
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extern void cmma_init(void);
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extern int memcpy_real(void *, void *, size_t);
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#define finish_arch_switch(prev) do { \
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set_fs(current->thread.mm_segment); \
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account_vtime(prev, current); \
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} while (0)
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#define nop() asm volatile("nop")
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#define xchg(ptr,x) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
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__ret; \
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})
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
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{
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unsigned long addr, old;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" (x << shift), "d" (~(255 << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" (x << shift), "d" (~(65535 << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 4:
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asm volatile(
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" l %0,%3\n"
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"0: cs %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) ptr)
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: "d" (x), "Q" (*(int *) ptr)
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: "memory", "cc");
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return old;
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#ifdef __s390x__
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case 8:
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asm volatile(
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" lg %0,%3\n"
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"0: csg %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(long *) ptr)
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: "d" (x), "Q" (*(long *) ptr)
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: "memory", "cc");
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return old;
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#endif /* __s390x__ */
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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unsigned long addr, prev, tmp;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
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: "d" (old << shift), "d" (new << shift),
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"d" (~(255 << shift)), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
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: "d" (old << shift), "d" (new << shift),
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"d" (~(65535 << shift)), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev >> shift;
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case 4:
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asm volatile(
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" cs %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(int *) ptr)
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: "0" (old), "d" (new), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev;
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#ifdef __s390x__
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case 8:
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asm volatile(
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" csg %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(long *) ptr)
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: "0" (old), "d" (new), "Q" (*(long *) ptr)
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: "memory", "cc");
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return prev;
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#endif /* __s390x__ */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* This is very similar to the ppc eieio/sync instruction in that is
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* does a checkpoint syncronisation & makes sure that
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* all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
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*/
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#define eieio() asm volatile("bcr 15,0" : : : "memory")
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#define SYNC_OTHER_CORES(x) eieio()
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#define mb() eieio()
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#define rmb() eieio()
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#define wmb() eieio()
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#define read_barrier_depends() do { } while(0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#ifdef __s390x__
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" lctlg %1,%2,%0\n" \
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: : "Q" (*(addrtype *)(&array)), \
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"i" (low), "i" (high)); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" stctg %1,%2,%0\n" \
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: "=Q" (*(addrtype *)(&array)) \
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: "i" (low), "i" (high)); \
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})
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#else /* __s390x__ */
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" lctl %1,%2,%0\n" \
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: : "Q" (*(addrtype *)(&array)), \
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"i" (low), "i" (high)); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" stctl %1,%2,%0\n" \
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: "=Q" (*(addrtype *)(&array)) \
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: "i" (low), "i" (high)); \
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})
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#endif /* __s390x__ */
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#define __ctl_set_bit(cr, bit) ({ \
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unsigned long __dummy; \
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__ctl_store(__dummy, cr, cr); \
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__dummy |= 1UL << (bit); \
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__ctl_load(__dummy, cr, cr); \
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})
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#define __ctl_clear_bit(cr, bit) ({ \
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unsigned long __dummy; \
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__ctl_store(__dummy, cr, cr); \
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__dummy &= ~(1UL << (bit)); \
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__ctl_load(__dummy, cr, cr); \
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})
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#include <linux/irqflags.h>
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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case 2:
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case 4:
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#ifdef __s390x__
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case 8:
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#endif
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return __cmpxchg(ptr, old, new, size);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#ifdef __s390x__
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#define cmpxchg64_local(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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cmpxchg_local((ptr), (o), (n)); \
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})
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#else
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#endif
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/*
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* Use to set psw mask except for the first byte which
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* won't be changed by this function.
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*/
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static inline void
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__set_psw_mask(unsigned long mask)
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{
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__load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
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}
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#define local_mcck_enable() __set_psw_mask(psw_kernel_bits)
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#define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
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#ifdef CONFIG_SMP
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extern void smp_ctl_set_bit(int cr, int bit);
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extern void smp_ctl_clear_bit(int cr, int bit);
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#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
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#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
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#else
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#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
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#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
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#endif /* CONFIG_SMP */
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static inline unsigned int stfl(void)
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{
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asm volatile(
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" .insn s,0xb2b10000,0(0)\n" /* stfl */
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"0:\n"
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EX_TABLE(0b,0b));
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return S390_lowcore.stfl_fac_list;
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}
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static inline int __stfle(unsigned long long *list, int doublewords)
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{
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typedef struct { unsigned long long _[doublewords]; } addrtype;
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register unsigned long __nr asm("0") = doublewords - 1;
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asm volatile(".insn s,0xb2b00000,%0" /* stfle */
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: "=m" (*(addrtype *) list), "+d" (__nr) : : "cc");
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return __nr + 1;
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}
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static inline int stfle(unsigned long long *list, int doublewords)
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{
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if (!(stfl() & (1UL << 24)))
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return -EOPNOTSUPP;
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return __stfle(list, doublewords);
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}
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static inline unsigned short stap(void)
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{
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unsigned short cpu_address;
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asm volatile("stap %0" : "=m" (cpu_address));
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return cpu_address;
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}
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extern void (*_machine_restart)(char *command);
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extern void (*_machine_halt)(void);
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extern void (*_machine_power_off)(void);
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#define arch_align_stack(x) (x)
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static inline int tprot(unsigned long addr)
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{
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int rc = -EFAULT;
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asm volatile(
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" tprot 0(%1),0\n"
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"0: ipm %0\n"
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" srl %0,28\n"
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"1:\n"
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EX_TABLE(0b,1b)
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: "+d" (rc) : "a" (addr) : "cc");
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return rc;
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}
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#endif /* __KERNEL__ */
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#endif
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