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kernel-fxtec-pro1x/include/asm-mips/mach-cobalt
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Ralf Baechle 641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:05 +01:00
..
cobalt.h [MIPS] Add GT641xx IRQ routines. 2007-10-11 23:46:04 +01:00
cpu-feature-overrides.h [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11 23:46:05 +01:00
irq.h [MIPS] Add GT641xx IRQ routines. 2007-10-11 23:46:04 +01:00
mach-gt64120.h [MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE 2006-11-30 01:14:43 +00:00