4060bbe993
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
32 lines
925 B
C
32 lines
925 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
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* Douglas Leung <douglas@mips.com>
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* Steven J. Hill <sjhill@mips.com>
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*/
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#ifndef _MIPS_SEAD3INT_H
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#define _MIPS_SEAD3INT_H
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#include <linux/irqchip/mips-gic.h>
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/* SEAD-3 GIC address space definitions. */
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#define GIC_BASE_ADDR 0x1b1c0000
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#define GIC_ADDRSPACE_SZ (128 * 1024)
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/* CPU interrupt offsets */
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#define CPU_INT_GIC 2
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#define CPU_INT_EHCI 2
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#define CPU_INT_UART0 4
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#define CPU_INT_UART1 4
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#define CPU_INT_NET 6
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/* GIC interrupt offsets */
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#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
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#define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2)
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#define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3)
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#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
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#endif /* !(_MIPS_SEAD3INT_H) */
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