60cd7e08e4
Introduce new macros for kernel load/store variants which will be used to perform regular kernel space load/store operations in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
184 lines
6.8 KiB
C
184 lines
6.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2014 Imagination Technologies Ltd.
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*
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*/
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#ifndef __ASM_ASM_EVA_H
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#define __ASM_ASM_EVA_H
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#ifndef __ASSEMBLY__
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/* Kernel variants */
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#define kernel_cache(op, base) "cache " op ", " base "\n"
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#define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
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#define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
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#define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
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#define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n"
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#define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n"
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#define kernel_lh(reg, addr) "lh " reg ", " addr "\n"
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#define kernel_lb(reg, addr) "lb " reg ", " addr "\n"
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#define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n"
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#define kernel_sw(reg, addr) "sw " reg ", " addr "\n"
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#define kernel_swl(reg, addr) "swl " reg ", " addr "\n"
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#define kernel_swr(reg, addr) "swr " reg ", " addr "\n"
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#define kernel_sh(reg, addr) "sh " reg ", " addr "\n"
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#define kernel_sb(reg, addr) "sb " reg ", " addr "\n"
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#ifdef CONFIG_32BIT
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/*
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* No 'sd' or 'ld' instructions in 32-bit but the code will
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* do the correct thing
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*/
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#define kernel_sd(reg, addr) user_sw(reg, addr)
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#define kernel_ld(reg, addr) user_lw(reg, addr)
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#else
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#define kernel_sd(reg, addr) "sd " reg", " addr "\n"
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#define kernel_ld(reg, addr) "ld " reg", " addr "\n"
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#endif /* CONFIG_32BIT */
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#ifdef CONFIG_EVA
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#define __BUILD_EVA_INSN(insn, reg, addr) \
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" .set push\n" \
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" .set mips0\n" \
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" .set eva\n" \
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" "insn" "reg", "addr "\n" \
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" .set pop\n"
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#define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base)
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#define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr)
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#define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr)
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#define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr)
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#define user_lwl(reg, addr) __BUILD_EVA_INSN("lwle", reg, addr)
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#define user_lwr(reg, addr) __BUILD_EVA_INSN("lwre", reg, addr)
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#define user_lh(reg, addr) __BUILD_EVA_INSN("lhe", reg, addr)
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#define user_lb(reg, addr) __BUILD_EVA_INSN("lbe", reg, addr)
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#define user_lbu(reg, addr) __BUILD_EVA_INSN("lbue", reg, addr)
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/* No 64-bit EVA instruction for loading double words */
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#define user_ld(reg, addr) user_lw(reg, addr)
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#define user_sw(reg, addr) __BUILD_EVA_INSN("swe", reg, addr)
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#define user_swl(reg, addr) __BUILD_EVA_INSN("swle", reg, addr)
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#define user_swr(reg, addr) __BUILD_EVA_INSN("swre", reg, addr)
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#define user_sh(reg, addr) __BUILD_EVA_INSN("she", reg, addr)
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#define user_sb(reg, addr) __BUILD_EVA_INSN("sbe", reg, addr)
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/* No 64-bit EVA instruction for storing double words */
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#define user_sd(reg, addr) user_sw(reg, addr)
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#else
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#define user_cache(op, base) kernel_cache(op, base)
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#define user_ll(reg, addr) kernel_ll(reg, addr)
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#define user_sc(reg, addr) kernel_sc(reg, addr)
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#define user_lw(reg, addr) kernel_lw(reg, addr)
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#define user_lwl(reg, addr) kernel_lwl(reg, addr)
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#define user_lwr(reg, addr) kernel_lwr(reg, addr)
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#define user_lh(reg, addr) kernel_lh(reg, addr)
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#define user_lb(reg, addr) kernel_lb(reg, addr)
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#define user_lbu(reg, addr) kernel_lbu(reg, addr)
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#define user_sw(reg, addr) kernel_sw(reg, addr)
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#define user_swl(reg, addr) kernel_swl(reg, addr)
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#define user_swr(reg, addr) kernel_swr(reg, addr)
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#define user_sh(reg, addr) kernel_sh(reg, addr)
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#define user_sb(reg, addr) kernel_sb(reg, addr)
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#ifdef CONFIG_32BIT
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#define user_sd(reg, addr) kernel_sw(reg, addr)
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#define user_ld(reg, addr) kernel_lw(reg, addr)
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#else
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#define user_sd(reg, addr) kernel_sd(reg, addr)
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#define user_ld(reg, addr) kernel_ld(reg, addr)
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#endif /* CONFIG_32BIT */
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#endif /* CONFIG_EVA */
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#else /* __ASSEMBLY__ */
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#define kernel_cache(op, base) cache op, base
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#define kernel_ll(reg, addr) ll reg, addr
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#define kernel_sc(reg, addr) sc reg, addr
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#define kernel_lw(reg, addr) lw reg, addr
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#define kernel_lwl(reg, addr) lwl reg, addr
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#define kernel_lwr(reg, addr) lwr reg, addr
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#define kernel_lh(reg, addr) lh reg, addr
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#define kernel_lb(reg, addr) lb reg, addr
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#define kernel_lbu(reg, addr) lbu reg, addr
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#define kernel_sw(reg, addr) sw reg, addr
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#define kernel_swl(reg, addr) swl reg, addr
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#define kernel_swr(reg, addr) swr reg, addr
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#define kernel_sh(reg, addr) sh reg, addr
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#define kernel_sb(reg, addr) sb reg, addr
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#ifdef CONFIG_32BIT
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/*
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* No 'sd' or 'ld' instructions in 32-bit but the code will
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* do the correct thing
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*/
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#define kernel_sd(reg, addr) user_sw(reg, addr)
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#define kernel_ld(reg, addr) user_lw(reg, addr)
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#else
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#define kernel_sd(reg, addr) sd reg, addr
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#define kernel_ld(reg, addr) ld reg, addr
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#endif /* CONFIG_32BIT */
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#ifdef CONFIG_EVA
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#define __BUILD_EVA_INSN(insn, reg, addr) \
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.set push; \
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.set mips0; \
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.set eva; \
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insn reg, addr; \
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.set pop;
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#define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base)
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#define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr)
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#define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr)
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#define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr)
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#define user_lwl(reg, addr) __BUILD_EVA_INSN(lwle, reg, addr)
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#define user_lwr(reg, addr) __BUILD_EVA_INSN(lwre, reg, addr)
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#define user_lh(reg, addr) __BUILD_EVA_INSN(lhe, reg, addr)
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#define user_lb(reg, addr) __BUILD_EVA_INSN(lbe, reg, addr)
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#define user_lbu(reg, addr) __BUILD_EVA_INSN(lbue, reg, addr)
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/* No 64-bit EVA instruction for loading double words */
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#define user_ld(reg, addr) user_lw(reg, addr)
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#define user_sw(reg, addr) __BUILD_EVA_INSN(swe, reg, addr)
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#define user_swl(reg, addr) __BUILD_EVA_INSN(swle, reg, addr)
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#define user_swr(reg, addr) __BUILD_EVA_INSN(swre, reg, addr)
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#define user_sh(reg, addr) __BUILD_EVA_INSN(she, reg, addr)
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#define user_sb(reg, addr) __BUILD_EVA_INSN(sbe, reg, addr)
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/* No 64-bit EVA instruction for loading double words */
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#define user_sd(reg, addr) user_sw(reg, addr)
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#else
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#define user_cache(op, base) kernel_cache(op, base)
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#define user_ll(reg, addr) kernel_ll(reg, addr)
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#define user_sc(reg, addr) kernel_sc(reg, addr)
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#define user_lw(reg, addr) kernel_lw(reg, addr)
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#define user_lwl(reg, addr) kernel_lwl(reg, addr)
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#define user_lwr(reg, addr) kernel_lwr(reg, addr)
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#define user_lh(reg, addr) kernel_lh(reg, addr)
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#define user_lb(reg, addr) kernel_lb(reg, addr)
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#define user_lbu(reg, addr) kernel_lbu(reg, addr)
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#define user_sw(reg, addr) kernel_sw(reg, addr)
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#define user_swl(reg, addr) kernel_swl(reg, addr)
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#define user_swr(reg, addr) kernel_swr(reg, addr)
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#define user_sh(reg, addr) kernel_sh(reg, addr)
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#define user_sb(reg, addr) kernel_sb(reg, addr)
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#ifdef CONFIG_32BIT
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#define user_sd(reg, addr) kernel_sw(reg, addr)
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#define user_ld(reg, addr) kernel_lw(reg, addr)
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#else
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#define user_sd(reg, addr) kernel_sd(reg, addr)
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#define user_ld(reg, addr) kernel_sd(reg, addr)
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#endif /* CONFIG_32BIT */
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#endif /* CONFIG_EVA */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ASM_EVA_H */
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