c45bd374e5
Otherwise we get the following error when enabling CONFIG_SMP for omap3_defconfig: arch/arm/kernel/entry-armv.S: Assembler messages: arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ipi r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ltirq r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ipi r0,r6,r5,lr' arch/arm/kernel/entry-armv.S:48: Error: bad instruction `test_for_ltirq r0,r6,r5,lr' Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
214 lines
5.6 KiB
ArmAsm
214 lines
5.6 KiB
ArmAsm
/*
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* arch/arm/plat-omap/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for OMAP-based platforms
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <mach/irqs.h>
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#include <asm/hardware/gic.h>
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#include <plat/omap24xx.h>
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#include <plat/omap34xx.h>
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#include <plat/omap44xx.h>
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#include <plat/multi.h>
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#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
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#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
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#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
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.macro disable_fiq
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* Unoptimized irq functions for multi-omap2, 3 and 4
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*/
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#ifdef MULTI_OMAP2
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.pushsection .data
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omap_irq_base: .word 0
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.popsection
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/* Configure the interrupt base on the first interrupt */
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.macro get_irqnr_preamble, base, tmp
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9:
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ldr \base, =omap_irq_base @ irq base address
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ldr \base, [\base, #0] @ irq base value
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cmp \base, #0 @ already configured?
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bne 9997f @ nothing to do
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mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
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and \tmp, \tmp, #0x000f0000 @ only check architecture
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cmp \tmp, #0x00070000 @ is v6?
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beq 2400f @ found v6 so it's omap24xx
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mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
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and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
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cmp \tmp, #0x00000080 @ cortex A-8?
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beq 3400f @ found A-8 so it's omap34xx
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cmp \tmp, #0x00000090 @ cortex A-9?
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beq 4400f @ found A-9 so it's omap44xx
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2400: ldr \base, =OMAP2_IRQ_BASE
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ldr \tmp, =omap_irq_base
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str \base, [\tmp, #0]
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b 9b
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3400: ldr \base, =OMAP3_IRQ_BASE
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ldr \tmp, =omap_irq_base
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str \base, [\tmp, #0]
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b 9b
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4400: ldr \base, =OMAP4_IRQ_BASE
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ldr \tmp, =omap_irq_base
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str \base, [\tmp, #0]
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b 9b
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9997:
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.endm
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/* Check the pending interrupts. Note that base already set */
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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tst \base, #0x100 @ gic address?
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bne 4401f @ found gic
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/* Handle omap2 and omap3 */
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 9998f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 9998f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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9998:
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ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
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and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
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b 9999f
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/* Handle omap4 */
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4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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9999:
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.endm
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#else /* MULTI_OMAP2 */
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/*
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* Optimized irq functions for omap2, 3 and 4
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*/
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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.macro get_irqnr_preamble, base, tmp
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#ifdef CONFIG_ARCH_OMAP2
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ldr \base, =OMAP2_IRQ_BASE
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#else
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ldr \base, =OMAP3_IRQ_BASE
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#endif
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.endm
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/* Check the pending interrupts. Note that base already set */
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 9999f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 9999f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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9999:
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ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
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and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
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.endm
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =OMAP4_IRQ_BASE
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an
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* interrupt if it's between 30 and 1020. The test_for_ipi
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* routine below will pick up on IPIs.
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* A simple read from the controller will tell us the number
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* of the highest priority enabled interrupt.
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* We then just need to check whether it is in the
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* valid range for an IRQ (30-1020 inclusive).
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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#endif
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#endif /* MULTI_OMAP2 */
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#ifdef CONFIG_SMP
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt
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* on the controller, since this requires the original irqstat
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* value which we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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it cc
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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it cs
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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itt eq
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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#endif /* CONFIG_SMP */
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.macro irq_prio_table
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.endm
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