1855a2c4ce
When we bring up a new CPU via INIT/startup IPI messages, the CPU that's coming up sends a xTPR message to the chipset. Intel chipsets (at least) don't provide any architectural guarantee on what the chipset will do with this message. For example, the E850x chipsets uses this xTPR message to interpret the interrupt operating mode of the platform. When the CPU coming online sends this message, it always indicates that it is in logical flat mode. For the CPU hotplug case, the platform may already be functioning in cluster APIC mode at this time, the chipset can get confused and mishandle I/O device and IPI interrupt routing. The situation eventually gets corrected when the new CPU sends another xTPR update when we switch it to cluster mode, but there's a window during which the chipset may be in an inconsistent state. This patch avoids this problem by using the flat physical interrupt delivery mode instead of cluster mode for bigsmp (>8 cpu) support. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
158 lines
3.4 KiB
C
158 lines
3.4 KiB
C
#ifndef __ASM_MACH_APIC_H
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#define __ASM_MACH_APIC_H
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extern u8 bios_cpu_apicid[];
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#define xapic_phys_to_log_apicid(cpu) (bios_cpu_apicid[cpu])
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#define esr_disable (1)
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static inline int apic_id_registered(void)
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{
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return (1);
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}
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/* Round robin the irqs amoung the online cpus */
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static inline cpumask_t target_cpus(void)
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{
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static unsigned long cpu = NR_CPUS;
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do {
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if (cpu >= NR_CPUS)
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cpu = first_cpu(cpu_online_map);
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else
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cpu = next_cpu(cpu, cpu_online_map);
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} while (cpu >= NR_CPUS);
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return cpumask_of_cpu(cpu);
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}
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#undef APIC_DEST_LOGICAL
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#define APIC_DEST_LOGICAL 0
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#define TARGET_CPUS (target_cpus())
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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#define INT_DELIVERY_MODE (dest_Fixed)
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#define INT_DEST_MODE (0) /* phys delivery to target proc */
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#define NO_BALANCE_IRQ (0)
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#define WAKE_SECONDARY_VIA_INIT
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return (0);
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}
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static inline unsigned long check_apicid_present(int bit)
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{
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return (1);
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}
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static inline unsigned long calculate_ldr(int cpu)
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{
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unsigned long val, id;
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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id = xapic_phys_to_log_apicid(cpu);
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val |= SET_APIC_LOGICAL_ID(id);
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return val;
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static inline void init_apic_ldr(void)
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{
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unsigned long val;
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int cpu = smp_processor_id();
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apic_write_around(APIC_DFR, APIC_DFR_VALUE);
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val = calculate_ldr(cpu);
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apic_write_around(APIC_LDR, val);
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}
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static inline void clustered_apic_check(void)
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{
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"Physflat", nr_ioapics);
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}
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static inline int multi_timer_check(int apic, int irq)
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{
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return (0);
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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return (0);
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS)
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return (int) bios_cpu_apicid[mps_cpu];
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return BAD_APICID;
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}
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static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
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{
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return physid_mask_of_physid(phys_apicid);
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}
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extern u8 cpu_2_logical_apicid[];
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/* Mapping from cpu number to logical apicid */
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static inline int cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= NR_CPUS)
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return BAD_APICID;
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return cpu_physical_id(cpu);
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}
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static inline int mpc_apic_id(struct mpc_config_processor *m,
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struct mpc_config_translation *translation_record)
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{
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printk("Processor #%d %ld:%ld APIC version %d\n",
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m->mpc_apicid,
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(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
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(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
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m->mpc_apicver);
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return m->mpc_apicid;
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
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{
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/* For clustered we don't have a good way to do this yet - hack */
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return physids_promote(0xFFL);
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}
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static inline void setup_portio_remap(void)
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{
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}
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static inline void enable_apic_mode(void)
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{
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}
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static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return (1);
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}
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/* As we are using single CPU as destination, pick only one CPU here */
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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int apicid;
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cpu = first_cpu(cpumask);
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apicid = cpu_to_logical_apicid(cpu);
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return apicid;
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}
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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#endif /* __ASM_MACH_APIC_H */
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