0d831770b1
This extends the current SH DMA API somewhat to support a proper virtual channel abstraction, and also works to represent this through the driver model by giving each DMAC its own platform device. There's also a few other minor changes to support a few new CPU subtypes, and make TEI generation for the SH DMAC configurable. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
49 lines
1,016 B
C
49 lines
1,016 B
C
#ifndef __ASM_CPU_SH4_DMA_H
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#define __ASM_CPU_SH4_DMA_H
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#ifdef CONFIG_CPU_SH4A
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#define SH_DMAC_BASE 0xfc808020
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#else
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#define SH_DMAC_BASE 0xffa00000
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#endif
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/* Definitions for the SuperH DMAC */
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#define TM_BURST 0x0000080
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#define TS_8 0x00000010
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#define TS_16 0x00000020
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#define TS_32 0x00000030
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#define TS_64 0x00000000
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#define CHCR_TS_MASK 0x30
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#define CHCR_TS_SHIFT 4
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#define DMAOR_COD 0x00000008
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#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
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* with their respective values as they appear in the CHCR registers.
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*
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* Defaults to a 64-bit transfer size.
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*/
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enum {
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XMIT_SZ_64BIT,
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_256BIT,
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};
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/*
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* The DMA count is defined as the number of bytes to transfer.
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*/
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static unsigned int ts_shift[] __attribute__ ((used)) = {
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[XMIT_SZ_64BIT] = 3,
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_256BIT] = 5,
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};
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#endif /* __ASM_CPU_SH4_DMA_H */
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