e06b86a33a
Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate for the appropriate clock. This is in preparation for migrating the clocks towards common clock framework & devicetree. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Apelete Seketeli <apelete@seketeli.net> Patchwork: https://patchwork.linux-mips.org/patch/10149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pm.h>
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#include <asm/reboot.h>
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#include <asm/mach-jz4740/base.h>
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#include <asm/mach-jz4740/timer.h>
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#include "reset.h"
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#include "clock.h"
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static void jz4740_halt(void)
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{
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while (1) {
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__asm__(".set push;\n"
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".set mips3;\n"
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"wait;\n"
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".set pop;\n"
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);
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}
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}
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#define JZ_REG_WDT_DATA 0x00
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#define JZ_REG_WDT_COUNTER_ENABLE 0x04
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#define JZ_REG_WDT_COUNTER 0x08
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#define JZ_REG_WDT_CTRL 0x0c
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static void jz4740_restart(char *command)
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{
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void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
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jz4740_timer_enable_watchdog();
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writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
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writew(0, wdt_base + JZ_REG_WDT_COUNTER);
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writew(0, wdt_base + JZ_REG_WDT_DATA);
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writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
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writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
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jz4740_halt();
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}
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#define JZ_REG_RTC_CTRL 0x00
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#define JZ_REG_RTC_HIBERNATE 0x20
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#define JZ_REG_RTC_WAKEUP_FILTER 0x24
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#define JZ_REG_RTC_RESET_COUNTER 0x28
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#define JZ_RTC_CTRL_WRDY BIT(7)
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#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
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#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
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static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base)
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{
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uint32_t ctrl;
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do {
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ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
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} while (!(ctrl & JZ_RTC_CTRL_WRDY));
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}
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static void jz4740_power_off(void)
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{
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void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38);
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unsigned long wakeup_filter_ticks;
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unsigned long reset_counter_ticks;
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struct clk *rtc_clk;
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unsigned long rtc_rate;
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rtc_clk = clk_get(NULL, "rtc");
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if (IS_ERR(rtc_clk))
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panic("unable to get RTC clock");
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rtc_rate = clk_get_rate(rtc_clk);
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clk_put(rtc_clk);
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/*
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* Set minimum wakeup pin assertion time: 100 ms.
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* Range is 0 to 2 sec if RTC is clocked at 32 kHz.
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*/
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wakeup_filter_ticks = (100 * rtc_rate) / 1000;
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if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
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wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
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else
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wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
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jz4740_rtc_wait_ready(rtc_base);
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writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER);
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/*
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* Set reset pin low-level assertion time after wakeup: 60 ms.
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* Range is 0 to 125 ms if RTC is clocked at 32 kHz.
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*/
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reset_counter_ticks = (60 * rtc_rate) / 1000;
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if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
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reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
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else
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reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
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jz4740_rtc_wait_ready(rtc_base);
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writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER);
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jz4740_rtc_wait_ready(rtc_base);
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writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
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jz4740_halt();
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}
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void jz4740_reset_init(void)
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{
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_machine_restart = jz4740_restart;
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_machine_halt = jz4740_halt;
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pm_power_off = jz4740_power_off;
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}
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