cdfc83075f
Pull MIPS updates from Ralf Baechle:
"The most notable new addition inside this pull request is the support
for MIPS's latest and greatest core called "inter/proAptiv". The
patch series describes this core as follows.
"The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit."
The platform specific patches touch all 3 Broadcom families. It adds
support for the new Broadcom/Netlogix XLP9xx Soc, building a common
BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
and full gpio button/led descriptions for BCM47xx.
The rest of the series are cleanups and bug fixes that are MIPS
generic and consist largely of changes that Imgtec/MIPS had published
in their linux-mti-3.10.git stable tree. Random other cleanups and
patches preparing code to be merged in 3.15"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
mips: select ARCH_MIGHT_HAVE_PC_SERIO
mips: delete non-required instances of include <linux/init.h>
MIPS: KVM: remove shadow_tlb code
MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
mips/ide: flush dcache also if icache does not snoop dcache
MIPS: BCM47XX: fix position of cpu_wait disabling
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
MIPS: ZBOOT: gather string functions into string.c
arch/mips/pci: don't check resource with devm_ioremap_resource
arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
bcma: gpio: don't cast u32 to unsigned long
ssb: gpio: add own IRQ domain
MIPS: BCM47XX: fix sparse warnings in board.c
MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
MIPS: BCM47XX: fix detection for some boards
MIPS: BCM47XX: Enable buttons support on SSB
MIPS: BCM47XX: Convert WNDR4500 to new syntax
MIPS: BCM47XX: Use "timer" trigger for status LEDs
...
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| .. | ||
| bcma_private.h | ||
| core.c | ||
| driver_chipcommon.c | ||
| driver_chipcommon_nflash.c | ||
| driver_chipcommon_pmu.c | ||
| driver_chipcommon_sflash.c | ||
| driver_gmac_cmn.c | ||
| driver_gpio.c | ||
| driver_mips.c | ||
| driver_pci.c | ||
| driver_pci_host.c | ||
| host_pci.c | ||
| host_soc.c | ||
| Kconfig | ||
| main.c | ||
| Makefile | ||
| README | ||
| scan.c | ||
| scan.h | ||
| sprom.c | ||
| TODO | ||
Broadcom introduced new bus as replacement for older SSB. It is based on AMBA, however from programming point of view there is nothing AMBA specific we use. Standard AMBA drivers are platform specific, have hardcoded addresses and use AMBA standard fields like CID and PID. In case of Broadcom's cards every device consists of: 1) Broadcom specific AMBA device. It is put on AMBA bus, but can not be treated as standard AMBA device. Reading it's CID or PID can cause machine lockup. 2) AMBA standard devices called ports or wrappers. They have CIDs (AMBA_CID) and PIDs (0x103BB369), but we do not use that info for anything. One of that devices is used for managing Broadcom specific core. Addresses of AMBA devices are not hardcoded in driver and have to be read from EPROM. In this situation we decided to introduce separated bus. It can contain up to 16 devices identified by Broadcom specific fields: manufacturer, id, revision and class.