e85d59df13
This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit will also lock the other blocks including UART. Instead of setting only the PLL soft reset bit in the software reset register, set this bit but do not touch the others. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
127 lines
2.8 KiB
C
127 lines
2.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/reboot.h>
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#include <asm/cacheflush.h>
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#include <bcm63xx_board.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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void bcm63xx_machine_halt(void)
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{
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printk(KERN_INFO "System halted\n");
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while (1)
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;
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}
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static void bcm6348_a1_reboot(void)
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{
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u32 reg;
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/* soft reset all blocks */
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printk(KERN_INFO "soft-reseting all blocks ...\n");
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reg = bcm_perf_readl(PERF_SOFTRESET_REG);
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reg &= ~SOFTRESET_6348_ALL;
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bcm_perf_writel(reg, PERF_SOFTRESET_REG);
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mdelay(10);
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reg = bcm_perf_readl(PERF_SOFTRESET_REG);
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reg |= SOFTRESET_6348_ALL;
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bcm_perf_writel(reg, PERF_SOFTRESET_REG);
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mdelay(10);
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/* Jump to the power on address. */
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printk(KERN_INFO "jumping to reset vector.\n");
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/* set high vectors (base at 0xbfc00000 */
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set_c0_status(ST0_BEV | ST0_ERL);
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/* run uncached in kseg0 */
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change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
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__flush_cache_all();
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/* remove all wired TLB entries */
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write_c0_wired(0);
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__asm__ __volatile__(
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"jr\t%0"
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:
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: "r" (0xbfc00000));
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while (1)
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;
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}
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void bcm63xx_machine_reboot(void)
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{
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u32 reg;
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/* mask and clear all external irq */
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg &= ~EXTIRQ_CFG_MASK_ALL;
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reg |= EXTIRQ_CFG_CLEAR_ALL;
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
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bcm6348_a1_reboot();
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printk(KERN_INFO "triggering watchdog soft-reset...\n");
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reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
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reg |= SYS_PLL_SOFT_RESET;
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bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
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while (1)
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;
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}
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static void __bcm63xx_machine_reboot(char *p)
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{
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bcm63xx_machine_reboot();
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}
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/*
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* return system type in /proc/cpuinfo
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*/
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const char *get_system_type(void)
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{
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static char buf[128];
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snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
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board_get_name(),
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bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
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return buf;
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}
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void __init plat_time_init(void)
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{
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mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
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}
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void __init plat_mem_setup(void)
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{
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add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
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_machine_halt = bcm63xx_machine_halt;
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_machine_restart = __bcm63xx_machine_reboot;
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pm_power_off = bcm63xx_machine_halt;
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set_io_port_base(0);
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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board_setup();
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}
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int __init bcm63xx_register_devices(void)
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{
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return board_register_devices();
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}
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arch_initcall(bcm63xx_register_devices);
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