6000fc4d6f
It is possible for the CPU to re-enable it's interrupt block bit before the write to the interrupt controller has actually masked out the external interupt at the controller. We get around this by reading back from the interrupt controller which will ensure the write has happened. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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| maple | ||
| superhyway | ||
| intc.c | ||
| Makefile | ||