2f1d489932
Most of these were previously used by numerous C files and redeclared in each one. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/*
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* Copyright 2007 David Gibson, IBM Corporation.
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*
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* Based on earlier code:
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* Copyright (C) Paul Mackerras 1997.
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*
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <stdarg.h>
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#include <stddef.h>
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#include "types.h"
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#include "elf.h"
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#include "string.h"
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#include "stdio.h"
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#include "page.h"
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#include "ops.h"
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#include "reg.h"
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#include "io.h"
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#include "dcr.h"
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#include "4xx.h"
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#include "44x.h"
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static u8 *ebony_mac0, *ebony_mac1;
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/* Calculate 440GP clocks */
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void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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{
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u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
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u32 cr0 = mfdcr(DCRN_CPC0_CR0);
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u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
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u32 opdv = CPC0_SYS0_OPDV(sys0);
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u32 epdv = CPC0_SYS0_EPDV(sys0);
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if (sys0 & CPC0_SYS0_BYPASS) {
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/* Bypass system PLL */
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cpu = plb = sysclk;
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} else {
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if (sys0 & CPC0_SYS0_EXTSL)
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/* PerClk */
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m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
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else
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/* CPU clock */
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m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
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cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0);
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plb = sysclk * m / CPC0_SYS0_FWDVB(sys0);
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}
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opb = plb / opdv;
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ebc = opb / epdv;
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/* FIXME: Check if this is for all 440GP, or just Ebony */
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if ((mfpvr() & 0xf0000fff) == 0x40000440)
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/* Rev. B 440GP, use external system clock */
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tb = sysclk;
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else
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/* Rev. C 440GP, errata force us to use internal clock */
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tb = cpu;
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if (cr0 & CPC0_CR0_U0EC)
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/* External UART clock */
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uart0 = ser_clk;
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else
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/* Internal UART clock */
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uart0 = plb / CPC0_CR0_UDIV(cr0);
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if (cr0 & CPC0_CR0_U1EC)
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/* External UART clock */
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uart1 = ser_clk;
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else
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/* Internal UART clock */
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uart1 = plb / CPC0_CR0_UDIV(cr0);
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printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
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(sysclk + 500000) / 1000000, sysclk);
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dt_fixup_cpu_clocks(cpu, tb, 0);
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dt_fixup_clock("/plb", plb);
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dt_fixup_clock("/plb/opb", opb);
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dt_fixup_clock("/plb/opb/ebc", ebc);
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dt_fixup_clock("/plb/opb/serial@40000200", uart0);
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dt_fixup_clock("/plb/opb/serial@40000300", uart1);
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}
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#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
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#define EBONY_FPGA_FLASH_SEL 0x01
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#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
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static void ebony_flashsel_fixup(void)
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{
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void *devp;
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u32 reg[3] = {0x0, 0x0, 0x80000};
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u8 *fpga;
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u8 fpga_reg0 = 0x0;
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devp = finddevice(EBONY_FPGA_PATH);
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if (!devp)
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fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH);
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if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
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fatal("%s has missing or invalid virtual-reg property\n\r",
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EBONY_FPGA_PATH);
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fpga_reg0 = in_8(fpga);
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devp = finddevice(EBONY_SMALL_FLASH_PATH);
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if (!devp)
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fatal("Couldn't locate small flash node %s\n\r",
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EBONY_SMALL_FLASH_PATH);
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if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg))
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fatal("%s has reg property of unexpected size\n\r",
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EBONY_SMALL_FLASH_PATH);
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/* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */
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if (fpga_reg0 & EBONY_FPGA_FLASH_SEL)
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reg[1] ^= 0x80000;
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setprop(devp, "reg", reg, sizeof(reg));
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}
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static void ebony_fixups(void)
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{
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// FIXME: sysclk should be derived by reading the FPGA registers
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unsigned long sysclk = 33000000;
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ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
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ibm4xx_fixup_memsize();
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dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
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ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
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ebony_flashsel_fixup();
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}
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void ebony_init(void *mac0, void *mac1)
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{
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platform_ops.fixups = ebony_fixups;
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platform_ops.exit = ibm44x_dbcr_reset;
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ebony_mac0 = mac0;
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ebony_mac1 = mac1;
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ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
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serial_console_init();
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}
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