ae8a8b9553
Many ARMv7 cores have hardware page table walkers that can read the L1 cache. This is discoverable from the ID_MMFR3 register, although this can be expensive to access from the low-level set_pte functions and is a pain to cache, particularly with multi-cluster systems. A useful observation is that the multi-processing extensions for ARMv7 require coherent table walks, meaning that we can make use of ALT_SMP patching in proc-v7-* to patch away the cache flush safely for these cores. Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
154 lines
4.5 KiB
ArmAsm
154 lines
4.5 KiB
ArmAsm
/*
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* arch/arm/mm/proc-v7-3level.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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* based on arch/arm/mm/proc-v7-2level.S
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define TTB_IRGN_NC (0 << 8)
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#define TTB_IRGN_WBWA (1 << 8)
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#define TTB_IRGN_WT (2 << 8)
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#define TTB_IRGN_WB (3 << 8)
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#define TTB_RGN_NC (0 << 10)
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#define TTB_RGN_OC_WBWA (1 << 10)
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#define TTB_RGN_OC_WT (2 << 10)
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#define TTB_RGN_OC_WB (3 << 10)
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#define TTB_S (3 << 12)
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#define TTB_EAE (1 << 31)
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB)
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#define PMD_FLAGS_UP (PMD_SECT_WB)
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
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#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S)
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys (physical address of
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* the new TTB).
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*/
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ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mmid r1, r1 @ get mm->context.id
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asid r3, r1
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mov r3, r3, lsl #(48 - 32) @ ASID
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mcrr p15, 0, r0, r3, c2 @ set TTB 0
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isb
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_switch_mm)
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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* - ptep - pointer to level 3 translation table entry
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* - pte - PTE value to store (64-bit in r2 and r3)
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*/
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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tst r2, #L_PTE_VALID
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beq 1f
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tst r3, #1 << (57 - 32) @ L_PTE_NONE
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bicne r2, #L_PTE_VALID
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bne 1f
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tst r3, #1 << (55 - 32) @ L_PTE_DIRTY
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orreq r2, #L_PTE_RDONLY
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1: strd r2, r3, [r0]
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ALT_SMP(mov pc, lr)
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ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_set_pte_ext)
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/*
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* Memory region attributes for LPAE (defined in pgtable-3level.h):
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*
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* n = AttrIndx[2:0]
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*
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* n MAIR
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* UNCACHED 000 00000000
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* BUFFERABLE 001 01000100
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* DEV_WC 001 01000100
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* WRITETHROUGH 010 10101010
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* WRITEBACK 011 11101110
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* DEV_CACHED 011 11101110
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* DEV_SHARED 100 00000100
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* DEV_NONSHARED 100 00000100
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* unused 101
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* unused 110
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* WRITEALLOC 111 11111111
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*/
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.equ PRRR, 0xeeaa4400 @ MAIR0
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.equ NMRR, 0xff000004 @ MAIR1
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/*
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* Macro for setting up the TTBRx and TTBCR registers.
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* - \ttbr1 updated.
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*/
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.macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
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ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
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cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
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mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register
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orr \tmp, \tmp, #TTB_EAE
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ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
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ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
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ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
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ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
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/*
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* TTBR0/TTBR1 split (PAGE_OFFSET):
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* 0x40000000: T0SZ = 2, T1SZ = 0 (not used)
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* 0x80000000: T0SZ = 0, T1SZ = 1
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* 0xc0000000: T0SZ = 0, T1SZ = 2
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*
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* Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
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* booting secondary CPUs would end up using TTBR1 for the identity
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* mapping set up in TTBR0.
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*/
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bhi 9001f @ PHYS_OFFSET > PAGE_OFFSET?
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orr \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
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#if defined CONFIG_VMSPLIT_2G
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/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
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add \ttbr1, \ttbr1, #1 << 4 @ skip two L1 entries
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#elif defined CONFIG_VMSPLIT_3G
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/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
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add \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
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#endif
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/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
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9001: mcr p15, 0, \tmp, c2, c0, 2 @ TTB control register
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mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
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.endm
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__CPUINIT
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/*
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* AT
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* TFR EV X F IHD LR S
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* .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
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* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 11 0 110 1 0011 1100 .111 1101 < we want
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*/
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.align 2
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.type v7_crval, #object
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v7_crval:
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crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
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.previous
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