5d9b4b19f1
If using 64-bit PTEs and 4K pages then each page table has 512 entries (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows the convention that all structures in the page table (pgd_t, pmd_t, pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require 64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs it is only possible to map 1GB of virtual address space. In order to map all 4GB of virtual address space we need to adopt a 3-level page table layout. This actually works out better for CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2 areas (which are untranslated) instead of 256. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
173 lines
4.2 KiB
C
173 lines
4.2 KiB
C
/*
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* This file contains the functions and defines necessary to modify and
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* use the SuperH page table tree.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of this
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* archive for more details.
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*/
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#ifndef __ASM_SH_PGTABLE_H
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#define __ASM_SH_PGTABLE_H
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#ifdef CONFIG_PGTABLE_LEVELS_3
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#include <asm/pgtable_pmd.h>
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#else
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#include <asm/pgtable_nopmd.h>
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#endif
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#include <asm/page.h>
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#ifndef __ASSEMBLY__
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#include <asm/addrspace.h>
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#include <asm/fixmap.h>
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#endif /* !__ASSEMBLY__ */
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/*
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* Effective and physical address definitions, to aid with sign
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* extension.
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*/
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#define NEFF 32
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#define NEFF_SIGN (1LL << (NEFF - 1))
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#define NEFF_MASK (-1LL << NEFF)
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static inline unsigned long long neff_sign_extend(unsigned long val)
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{
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unsigned long long extended = val;
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return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
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}
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#ifdef CONFIG_29BIT
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#define NPHYS 29
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#else
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#define NPHYS 32
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#endif
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#define NPHYS_SIGN (1LL << (NPHYS - 1))
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#define NPHYS_MASK (-1LL << NPHYS)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Entries per level */
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#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
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#define FIRST_USER_ADDRESS 0
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#define PHYS_ADDR_MASK29 0x1fffffff
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#define PHYS_ADDR_MASK32 0xffffffff
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#ifdef CONFIG_PMB
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static inline unsigned long phys_addr_mask(void)
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{
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/* Is the MMU in 29bit mode? */
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if (__in_29bit_mode())
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return PHYS_ADDR_MASK29;
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return PHYS_ADDR_MASK32;
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}
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#elif defined(CONFIG_32BIT)
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static inline unsigned long phys_addr_mask(void)
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{
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return PHYS_ADDR_MASK32;
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}
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#else
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static inline unsigned long phys_addr_mask(void)
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{
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return PHYS_ADDR_MASK29;
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}
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#endif
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#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
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#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
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#ifdef CONFIG_SUPERH32
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#define VMALLOC_START (P3SEG)
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#else
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#define VMALLOC_START (0xf0000000)
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#endif
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#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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#if defined(CONFIG_SUPERH32)
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#include <asm/pgtable_32.h>
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#else
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#include <asm/pgtable_64.h>
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#endif
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/*
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* SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
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* protection for execute, and considers it the same as a read. Also, write
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* permission implies read permission. This is the closest we can get..
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*
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* SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
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* not only supporting separate execute, read, and write bits, but having
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* completely separate permission bits for user and kernel space.
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*/
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/*xwr*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_EXECREAD
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#define __P101 PAGE_EXECREAD
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_WRITEONLY
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_EXECREAD
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#define __S101 PAGE_EXECREAD
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#define __S110 PAGE_RWX
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#define __S111 PAGE_RWX
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typedef pte_t *pte_addr_t;
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#define kern_addr_valid(addr) (1)
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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struct vm_area_struct;
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extern void __update_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t pte);
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extern void __update_tlb(struct vm_area_struct *vma,
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unsigned long address, pte_t pte);
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static inline void
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update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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__update_cache(vma, address, pte);
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__update_tlb(vma, address, pte);
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}
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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extern void paging_init(void);
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extern void page_table_range_init(unsigned long start, unsigned long end,
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pgd_t *pgd);
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/* arch/sh/mm/mmap.c */
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#include <asm-generic/pgtable.h>
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#endif /* __ASM_SH_PGTABLE_H */
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