dfc25e4503
These cleanup patches are mainly move stuff around and should all be harmless. They are mainly split out so that other branches can be based on top to avoid conflicts. Notable changes are: * We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no longer used. (Uwe Kleine-König) * The Qualcomm MSM platform is split out into legacy mach-msm and new-style mach-qcom, to allow easier maintainance of the new hardware support without regressions. (Kumar Gala) * A rework of some of the Kconfig logic to simplify multiplatform support (Rob Herring) * Samsung Exynos gets closer to supporting multiplatform (Sachin Kamat and others) * mach-bcm3528 gets merged into mach-bcm (Stephen Warren) * at91 gains some common clock framework support (Alexandre Belloni, Jean-Jacques Hiblot and other French people). -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/yOWCrR//JCVInAQLOPBAAwTMkMrD8S8ggz6vfiQHZNdRPAC7NUJ46 +eYKmBVi5d6EdnjNuRElWENsh0ZosSAUFHrXsIC2NdH9sAJ9HOqWNNLymuA59Jo9 HZ/Ze6xQXDPNV7TROPoXuIli/2OCOXyyQHJsfI7h9V3PCx31qo0B5OdCxU0mtXK6 r1giREhnJFwfQMF/FTdnzhalFJoSjWwv/nkpNmQDJKRLKj9GzwQqItqw68gV6RzU Gnt6YK+9xC1B0cfWTFhAm6kbr9i7mvHoMG5tE3no2uuJMn4K7TgeMqOyvPWhmUeB EZi656szT1m5VfRWOqG+7coZO2VM4GO4NI0Xfin3GHllugOYls1il/FAfCPMLiwh RvuOmQGCkLIpdkuHop5QaI/h1EzlHA59nzTjmGf1+wWPsm0CIg08XOD9izQbRnN9 EmRqn1/8POIi17xcWyeMp8LB0APsTI+IflZFaYprEY9VlLLA/Pd+7udULhs8Bq8y 1l6fB6aPZKnDKCBy/PEIR+y+EHFEbwfrx6zm/pxVDX6P5DlQMFWL78pdBoJUa2h8 3pm/bSzNU5OSz1nJMLJv2jBTtnM5BvFgQBUi2qJ9Lr+nUhJXKCJ80kE/nOlXoCIU J952p3OhkYTQQcjuUVQeTXvRUOGB7mKok0pDFZNE6c7faqxTCudMABQq/KbMFstU eE3cH5FyYj4= =GcBb -----END PGP SIGNATURE----- Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Arnd Bergmann: "These cleanup patches are mainly move stuff around and should all be harmless. They are mainly split out so that other branches can be based on top to avoid conflicts. Notable changes are: - We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no longer used (Uwe Kleine-König) - The Qualcomm MSM platform is split out into legacy mach-msm and new-style mach-qcom, to allow easier maintainance of the new hardware support without regressions (Kumar Gala) - A rework of some of the Kconfig logic to simplify multiplatform support (Rob Herring) - Samsung Exynos gets closer to supporting multiplatform (Sachin Kamat and others) - mach-bcm3528 gets merged into mach-bcm (Stephen Warren) - at91 gains some common clock framework support (Alexandre Belloni, Jean-Jacques Hiblot and other French people)" * tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits) ARM: hisi: select HAVE_ARM_SCU only for SMP ARM: efm32: allow uncompress debug output ARM: prima2: build reset code standalone ARM: at91: add PWM clock ARM: at91: move sam9261 SoC to common clk ARM: at91: prepare common clk transition for sam9261 SoC ARM: at91: updated the at91_dt_defconfig with support for the ADS7846 ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs ARM: at91: dt: Add at91sam9261 dt SoC support ARM: at91: switch sam9rl to common clock framework ARM: at91/dt: define main clk frequency of at91sam9rlek ARM: at91/dt: define at91sam9rl clocks ARM: at91: prepare common clk transition for sam9rl SoCs ARM: at91: prepare sam9 dt boards transition to common clk ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs ARM: at91: Add at91sam9rl DT SoC support ARM: at91: prepare at91sam9rl DT transition ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig ...
247 lines
5.3 KiB
C
247 lines
5.3 KiB
C
/*
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* linux/arch/arm/mach-mmp/time.c
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*
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* Support for clocksource and clockevents
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*
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* Copyright (C) 2008 Marvell International Ltd.
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* All rights reserved.
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*
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* 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
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* 2008-10-08: Bin Yang <bin.yang@marvell.com>
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*
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* The timers module actually includes three timers, each timer with up to
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* three match comparators. Timer #0 is used here in free-running mode as
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* the clock source, and match comparator #1 used as clock event device.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <mach/addr-map.h>
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#include <mach/regs-timers.h>
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#include <mach/regs-apbc.h>
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#include <mach/irqs.h>
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#include <mach/cputype.h>
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#include <asm/mach/time.h>
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#include "clock.h"
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#ifdef CONFIG_CPU_MMP2
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#define MMP_CLOCK_FREQ 6500000
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#else
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#define MMP_CLOCK_FREQ 3250000
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#endif
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#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
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#define MAX_DELTA (0xfffffffe)
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#define MIN_DELTA (16)
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static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
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/*
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* FIXME: the timer needs some delay to stablize the counter capture
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*/
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static inline uint32_t timer_read(void)
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{
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int delay = 100;
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__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
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while (delay--)
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cpu_relax();
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return __raw_readl(mmp_timer_base + TMR_CVWR(1));
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}
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static u64 notrace mmp_read_sched_clock(void)
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{
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return timer_read();
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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/*
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* Clear pending interrupt status.
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*/
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__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, mmp_timer_base + TMR_CER);
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c->event_handler(c);
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return IRQ_HANDLED;
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}
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static int timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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unsigned long flags;
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local_irq_save(flags);
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, mmp_timer_base + TMR_CER);
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/*
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* Clear and enable timer match 0 interrupt.
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*/
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__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
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__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
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/*
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* Setup new clockevent timer value.
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*/
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__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
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/*
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* Enable timer 0.
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*/
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__raw_writel(0x03, mmp_timer_base + TMR_CER);
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local_irq_restore(flags);
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return 0;
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}
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static void timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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unsigned long flags;
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local_irq_save(flags);
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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/* disable the matching interrupt */
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__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
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break;
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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}
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local_irq_restore(flags);
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}
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static struct clock_event_device ckevt = {
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.name = "clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = timer_set_next_event,
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.set_mode = timer_set_mode,
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};
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static cycle_t clksrc_read(struct clocksource *cs)
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{
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return timer_read();
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}
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static struct clocksource cksrc = {
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.name = "clocksource",
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.rating = 200,
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.read = clksrc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init timer_config(void)
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{
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uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
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__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
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ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
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__raw_writel(ccr, mmp_timer_base + TMR_CCR);
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/* set timer 0 to periodic mode, and timer 1 to free-running mode */
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__raw_writel(0x2, mmp_timer_base + TMR_CMR);
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__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
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__raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
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__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
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__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
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__raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
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__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
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/* enable timer 1 counter */
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__raw_writel(0x2, mmp_timer_base + TMR_CER);
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}
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static struct irqaction timer_irq = {
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.name = "timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = timer_interrupt,
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.dev_id = &ckevt,
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};
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void __init timer_init(int irq)
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{
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timer_config();
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sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
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ckevt.cpumask = cpumask_of(0);
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setup_irq(irq, &timer_irq);
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clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
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clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
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MIN_DELTA, MAX_DELTA);
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}
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#ifdef CONFIG_OF
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static struct of_device_id mmp_timer_dt_ids[] = {
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{ .compatible = "mrvl,mmp-timer", },
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{}
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};
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void __init mmp_dt_init_timer(void)
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{
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struct device_node *np;
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int irq, ret;
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np = of_find_matching_node(NULL, mmp_timer_dt_ids);
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if (!np) {
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ret = -ENODEV;
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goto out;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -EINVAL;
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goto out;
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}
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mmp_timer_base = of_iomap(np, 0);
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if (!mmp_timer_base) {
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ret = -ENOMEM;
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goto out;
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}
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timer_init(irq);
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return;
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out:
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pr_err("Failed to get timer from device tree with error:%d\n", ret);
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}
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#endif
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