6cd94d5e57
New and updated SoC support, notable changes include: * bcm: brcmstb SMP support * bcm: initial iproc/cygnus support * exynos: Exynos4415 SoC support * exynos: PMU and suspend support for Exynos5420 * exynos: PMU support for Exynos3250 * exynos: pm related maintenance * imx: new LS1021A SoC support * imx: vybrid 610 global timer support * integrator: convert to using multiplatform configuration * mediatek: earlyprintk support for mt8127/mt8135 * meson: meson8 soc and l2 cache controller support * mvebu: Armada 38x CPU hotplug support * mvebu: drop support for prerelease Armada 375 Z1 stepping * mvebu: extended suspend support, now works on Armada 370/XP * omap: hwmod related maintenance * omap: prcm cleanup * pxa: initial pxa27x DT handling * rockchip: SMP support for rk3288 * rockchip: add cpu frequency scaling support * shmobile: r8a7740 power domain support * shmobile: various small restart, timer, pci apmu changes * sunxi: Allwinner A80 (sun9i) earlyprintk support * ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1 W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW 5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8 sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz +324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+ dF1lnQ7CXLQ= =lFoH -----END PGP SIGNATURE----- Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ...
162 lines
4.4 KiB
C
162 lines
4.4 KiB
C
/*
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* Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_COMMON_H__
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#define __ASM_ARCH_MXC_COMMON_H__
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#include <linux/reboot.h>
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struct irq_data;
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struct platform_device;
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struct pt_regs;
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struct clk;
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struct device_node;
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enum mxc_cpu_pwr_mode;
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struct of_device_id;
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void mx1_map_io(void);
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void mx21_map_io(void);
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void mx25_map_io(void);
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void mx27_map_io(void);
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void mx31_map_io(void);
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void mx35_map_io(void);
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void imx1_init_early(void);
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void imx21_init_early(void);
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void imx25_init_early(void);
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void imx27_init_early(void);
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void imx31_init_early(void);
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void imx35_init_early(void);
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void mxc_init_irq(void __iomem *);
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void tzic_init_irq(void);
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void mx1_init_irq(void);
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void mx21_init_irq(void);
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void mx25_init_irq(void);
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void mx27_init_irq(void);
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void mx31_init_irq(void);
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void mx35_init_irq(void);
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void imx1_soc_init(void);
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void imx21_soc_init(void);
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void imx25_soc_init(void);
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void imx27_soc_init(void);
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void imx31_soc_init(void);
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void imx35_soc_init(void);
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void epit_timer_init(void __iomem *base, int irq);
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void mxc_timer_init(void __iomem *, int);
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int mx1_clocks_init(unsigned long fref);
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int mx21_clocks_init(unsigned long lref, unsigned long fref);
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int mx25_clocks_init(void);
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int mx27_clocks_init(unsigned long fref);
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int mx31_clocks_init(unsigned long fref);
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int mx35_clocks_init(void);
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int mx31_clocks_init_dt(void);
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struct platform_device *mxc_register_gpio(char *name, int id,
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resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
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void mxc_set_cpu_type(unsigned int type);
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void mxc_restart(enum reboot_mode, const char *);
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void mxc_arch_reset_init(void __iomem *);
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int mx51_revision(void);
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int mx53_revision(void);
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void imx_set_aips(void __iomem *);
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void imx_aips_allow_unprivileged_access(const char *compat);
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int mxc_device_init(void);
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void imx_set_soc_revision(unsigned int rev);
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unsigned int imx_get_soc_revision(void);
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void imx_init_revision_from_anatop(void);
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struct device *imx_soc_device_init(void);
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enum mxc_cpu_pwr_mode {
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WAIT_CLOCKED, /* wfi only */
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WAIT_UNCLOCKED, /* WAIT */
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WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
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STOP_POWER_ON, /* just STOP */
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STOP_POWER_OFF, /* STOP + SRPG */
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};
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enum mx3_cpu_pwr_mode {
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MX3_RUN,
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MX3_WAIT,
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MX3_DOZE,
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MX3_SLEEP,
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};
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void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
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void imx_print_silicon_rev(const char *cpu, int srev);
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void imx_enable_cpu(int cpu, bool enable);
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void imx_set_cpu_jump(int cpu, void *jump_addr);
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u32 imx_get_cpu_arg(int cpu);
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void imx_set_cpu_arg(int cpu, u32 arg);
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#ifdef CONFIG_SMP
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void v7_secondary_startup(void);
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void imx_scu_map_io(void);
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void imx_smp_prepare(void);
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#else
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static inline void imx_scu_map_io(void) {}
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static inline void imx_smp_prepare(void) {}
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#endif
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void imx_src_init(void);
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void imx_gpc_init(void);
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void imx_gpc_pre_suspend(bool arm_power_off);
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void imx_gpc_post_resume(void);
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void imx_gpc_mask_all(void);
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void imx_gpc_restore_all(void);
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void imx_gpc_hwirq_mask(unsigned int hwirq);
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void imx_gpc_hwirq_unmask(unsigned int hwirq);
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void imx_anatop_init(void);
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void imx_anatop_pre_suspend(void);
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void imx_anatop_post_resume(void);
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int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
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void imx6q_set_int_mem_clk_lpm(bool enable);
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void imx6sl_set_wait_clk(bool enter);
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int imx_mmdc_get_ddr_type(void);
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void imx_cpu_die(unsigned int cpu);
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int imx_cpu_kill(unsigned int cpu);
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#ifdef CONFIG_SUSPEND
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void v7_cpu_resume(void);
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void imx6_suspend(void __iomem *ocram_vbase);
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#else
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static inline void v7_cpu_resume(void) {}
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static inline void imx6_suspend(void __iomem *ocram_vbase) {}
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#endif
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void imx6q_pm_init(void);
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void imx6dl_pm_init(void);
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void imx6sl_pm_init(void);
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void imx6sx_pm_init(void);
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void imx6q_pm_set_ccm_base(void __iomem *base);
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#ifdef CONFIG_PM
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void imx51_pm_init(void);
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void imx53_pm_init(void);
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void imx5_pm_set_ccm_base(void __iomem *base);
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#else
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static inline void imx51_pm_init(void) {}
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static inline void imx53_pm_init(void) {}
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static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
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#endif
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#ifdef CONFIG_NEON
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int mx51_neon_fixup(void);
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#else
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static inline int mx51_neon_fixup(void) { return 0; }
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#endif
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#ifdef CONFIG_CACHE_L2X0
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void imx_init_l2cache(void);
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#else
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static inline void imx_init_l2cache(void) {}
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#endif
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extern struct smp_operations imx_smp_ops;
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extern struct smp_operations ls1021a_smp_ops;
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#endif
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