fb97a84665
Allow the device tree to provide the mac address and the phy mode. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> [nicolas.ferre@atmel.com: change "compatible" node property, doc and DT hwaddr] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> [jamie@jamieiles.com: add "gem" compatibility strings and doc] Acked-by: Jamie Iles<jamie@jamieiles.com> Acked-by: David S. Miller <davem@davemloft.net>
544 lines
14 KiB
C
544 lines
14 KiB
C
/*
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* Atmel MACB Ethernet Controller driver
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _MACB_H
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#define _MACB_H
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/* MACB register offsets */
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#define MACB_NCR 0x0000
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#define MACB_NCFGR 0x0004
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#define MACB_NSR 0x0008
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#define MACB_TSR 0x0014
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#define MACB_RBQP 0x0018
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#define MACB_TBQP 0x001c
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#define MACB_RSR 0x0020
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#define MACB_ISR 0x0024
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#define MACB_IER 0x0028
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#define MACB_IDR 0x002c
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#define MACB_IMR 0x0030
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#define MACB_MAN 0x0034
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#define MACB_PTR 0x0038
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#define MACB_PFR 0x003c
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#define MACB_FTO 0x0040
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#define MACB_SCF 0x0044
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#define MACB_MCF 0x0048
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#define MACB_FRO 0x004c
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#define MACB_FCSE 0x0050
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#define MACB_ALE 0x0054
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#define MACB_DTF 0x0058
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#define MACB_LCOL 0x005c
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#define MACB_EXCOL 0x0060
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#define MACB_TUND 0x0064
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#define MACB_CSE 0x0068
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#define MACB_RRE 0x006c
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#define MACB_ROVR 0x0070
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#define MACB_RSE 0x0074
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#define MACB_ELE 0x0078
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#define MACB_RJA 0x007c
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#define MACB_USF 0x0080
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#define MACB_STE 0x0084
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#define MACB_RLE 0x0088
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#define MACB_TPF 0x008c
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#define MACB_HRB 0x0090
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#define MACB_HRT 0x0094
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#define MACB_SA1B 0x0098
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#define MACB_SA1T 0x009c
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#define MACB_SA2B 0x00a0
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#define MACB_SA2T 0x00a4
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#define MACB_SA3B 0x00a8
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#define MACB_SA3T 0x00ac
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#define MACB_SA4B 0x00b0
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#define MACB_SA4T 0x00b4
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#define MACB_TID 0x00b8
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#define MACB_TPQ 0x00bc
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#define MACB_USRIO 0x00c0
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#define MACB_WOL 0x00c4
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#define MACB_MID 0x00fc
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/* GEM register offsets. */
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#define GEM_NCFGR 0x0004
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#define GEM_USRIO 0x000c
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#define GEM_DMACFG 0x0010
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#define GEM_HRB 0x0080
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#define GEM_HRT 0x0084
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#define GEM_SA1B 0x0088
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#define GEM_SA1T 0x008C
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#define GEM_OTX 0x0100
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#define GEM_DCFG1 0x0280
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#define GEM_DCFG2 0x0284
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#define GEM_DCFG3 0x0288
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#define GEM_DCFG4 0x028c
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#define GEM_DCFG5 0x0290
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#define GEM_DCFG6 0x0294
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#define GEM_DCFG7 0x0298
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/* Bitfields in NCR */
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#define MACB_LB_OFFSET 0
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#define MACB_LB_SIZE 1
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#define MACB_LLB_OFFSET 1
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#define MACB_LLB_SIZE 1
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#define MACB_RE_OFFSET 2
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#define MACB_RE_SIZE 1
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#define MACB_TE_OFFSET 3
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#define MACB_TE_SIZE 1
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#define MACB_MPE_OFFSET 4
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#define MACB_MPE_SIZE 1
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#define MACB_CLRSTAT_OFFSET 5
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#define MACB_CLRSTAT_SIZE 1
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#define MACB_INCSTAT_OFFSET 6
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#define MACB_INCSTAT_SIZE 1
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#define MACB_WESTAT_OFFSET 7
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#define MACB_WESTAT_SIZE 1
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#define MACB_BP_OFFSET 8
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#define MACB_BP_SIZE 1
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#define MACB_TSTART_OFFSET 9
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#define MACB_TSTART_SIZE 1
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#define MACB_THALT_OFFSET 10
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#define MACB_THALT_SIZE 1
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#define MACB_NCR_TPF_OFFSET 11
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#define MACB_NCR_TPF_SIZE 1
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#define MACB_TZQ_OFFSET 12
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#define MACB_TZQ_SIZE 1
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/* Bitfields in NCFGR */
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#define MACB_SPD_OFFSET 0
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#define MACB_SPD_SIZE 1
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#define MACB_FD_OFFSET 1
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#define MACB_FD_SIZE 1
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#define MACB_BIT_RATE_OFFSET 2
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#define MACB_BIT_RATE_SIZE 1
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#define MACB_JFRAME_OFFSET 3
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#define MACB_JFRAME_SIZE 1
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#define MACB_CAF_OFFSET 4
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#define MACB_CAF_SIZE 1
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#define MACB_NBC_OFFSET 5
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#define MACB_NBC_SIZE 1
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#define MACB_NCFGR_MTI_OFFSET 6
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#define MACB_NCFGR_MTI_SIZE 1
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#define MACB_UNI_OFFSET 7
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#define MACB_UNI_SIZE 1
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#define MACB_BIG_OFFSET 8
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#define MACB_BIG_SIZE 1
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#define MACB_EAE_OFFSET 9
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#define MACB_EAE_SIZE 1
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#define MACB_CLK_OFFSET 10
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#define MACB_CLK_SIZE 2
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#define MACB_RTY_OFFSET 12
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#define MACB_RTY_SIZE 1
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#define MACB_PAE_OFFSET 13
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#define MACB_PAE_SIZE 1
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#define MACB_RBOF_OFFSET 14
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#define MACB_RBOF_SIZE 2
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#define MACB_RLCE_OFFSET 16
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#define MACB_RLCE_SIZE 1
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#define MACB_DRFCS_OFFSET 17
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#define MACB_DRFCS_SIZE 1
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#define MACB_EFRHD_OFFSET 18
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#define MACB_EFRHD_SIZE 1
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#define MACB_IRXFCS_OFFSET 19
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#define MACB_IRXFCS_SIZE 1
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/* GEM specific NCFGR bitfields. */
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#define GEM_CLK_OFFSET 18
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#define GEM_CLK_SIZE 3
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#define GEM_DBW_OFFSET 21
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#define GEM_DBW_SIZE 2
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/* Constants for data bus width. */
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#define GEM_DBW32 0
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#define GEM_DBW64 1
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#define GEM_DBW128 2
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/* Bitfields in DMACFG. */
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#define GEM_RXBS_OFFSET 16
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#define GEM_RXBS_SIZE 8
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/* Bitfields in NSR */
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#define MACB_NSR_LINK_OFFSET 0
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#define MACB_NSR_LINK_SIZE 1
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#define MACB_MDIO_OFFSET 1
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#define MACB_MDIO_SIZE 1
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#define MACB_IDLE_OFFSET 2
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#define MACB_IDLE_SIZE 1
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/* Bitfields in TSR */
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#define MACB_UBR_OFFSET 0
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#define MACB_UBR_SIZE 1
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#define MACB_COL_OFFSET 1
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#define MACB_COL_SIZE 1
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#define MACB_TSR_RLE_OFFSET 2
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#define MACB_TSR_RLE_SIZE 1
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#define MACB_TGO_OFFSET 3
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#define MACB_TGO_SIZE 1
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#define MACB_BEX_OFFSET 4
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#define MACB_BEX_SIZE 1
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#define MACB_COMP_OFFSET 5
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#define MACB_COMP_SIZE 1
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#define MACB_UND_OFFSET 6
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#define MACB_UND_SIZE 1
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/* Bitfields in RSR */
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#define MACB_BNA_OFFSET 0
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#define MACB_BNA_SIZE 1
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#define MACB_REC_OFFSET 1
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#define MACB_REC_SIZE 1
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#define MACB_OVR_OFFSET 2
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#define MACB_OVR_SIZE 1
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/* Bitfields in ISR/IER/IDR/IMR */
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#define MACB_MFD_OFFSET 0
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#define MACB_MFD_SIZE 1
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#define MACB_RCOMP_OFFSET 1
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#define MACB_RCOMP_SIZE 1
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#define MACB_RXUBR_OFFSET 2
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#define MACB_RXUBR_SIZE 1
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#define MACB_TXUBR_OFFSET 3
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#define MACB_TXUBR_SIZE 1
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#define MACB_ISR_TUND_OFFSET 4
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#define MACB_ISR_TUND_SIZE 1
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#define MACB_ISR_RLE_OFFSET 5
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#define MACB_ISR_RLE_SIZE 1
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#define MACB_TXERR_OFFSET 6
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#define MACB_TXERR_SIZE 1
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#define MACB_TCOMP_OFFSET 7
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#define MACB_TCOMP_SIZE 1
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#define MACB_ISR_LINK_OFFSET 9
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#define MACB_ISR_LINK_SIZE 1
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#define MACB_ISR_ROVR_OFFSET 10
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#define MACB_ISR_ROVR_SIZE 1
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#define MACB_HRESP_OFFSET 11
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#define MACB_HRESP_SIZE 1
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#define MACB_PFR_OFFSET 12
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#define MACB_PFR_SIZE 1
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#define MACB_PTZ_OFFSET 13
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#define MACB_PTZ_SIZE 1
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/* Bitfields in MAN */
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#define MACB_DATA_OFFSET 0
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#define MACB_DATA_SIZE 16
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#define MACB_CODE_OFFSET 16
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#define MACB_CODE_SIZE 2
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#define MACB_REGA_OFFSET 18
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#define MACB_REGA_SIZE 5
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#define MACB_PHYA_OFFSET 23
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#define MACB_PHYA_SIZE 5
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#define MACB_RW_OFFSET 28
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#define MACB_RW_SIZE 2
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#define MACB_SOF_OFFSET 30
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#define MACB_SOF_SIZE 2
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/* Bitfields in USRIO (AVR32) */
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#define MACB_MII_OFFSET 0
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#define MACB_MII_SIZE 1
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#define MACB_EAM_OFFSET 1
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#define MACB_EAM_SIZE 1
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#define MACB_TX_PAUSE_OFFSET 2
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#define MACB_TX_PAUSE_SIZE 1
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#define MACB_TX_PAUSE_ZERO_OFFSET 3
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#define MACB_TX_PAUSE_ZERO_SIZE 1
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/* Bitfields in USRIO (AT91) */
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#define MACB_RMII_OFFSET 0
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#define MACB_RMII_SIZE 1
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#define MACB_CLKEN_OFFSET 1
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#define MACB_CLKEN_SIZE 1
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/* Bitfields in WOL */
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#define MACB_IP_OFFSET 0
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#define MACB_IP_SIZE 16
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#define MACB_MAG_OFFSET 16
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#define MACB_MAG_SIZE 1
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#define MACB_ARP_OFFSET 17
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#define MACB_ARP_SIZE 1
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#define MACB_SA1_OFFSET 18
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#define MACB_SA1_SIZE 1
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#define MACB_WOL_MTI_OFFSET 19
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#define MACB_WOL_MTI_SIZE 1
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/* Bitfields in MID */
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#define MACB_IDNUM_OFFSET 16
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#define MACB_IDNUM_SIZE 16
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#define MACB_REV_OFFSET 0
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#define MACB_REV_SIZE 16
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/* Bitfields in DCFG1. */
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#define GEM_DBWDEF_OFFSET 25
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#define GEM_DBWDEF_SIZE 3
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/* Constants for CLK */
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#define MACB_CLK_DIV8 0
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#define MACB_CLK_DIV16 1
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#define MACB_CLK_DIV32 2
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#define MACB_CLK_DIV64 3
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/* GEM specific constants for CLK. */
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#define GEM_CLK_DIV8 0
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#define GEM_CLK_DIV16 1
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#define GEM_CLK_DIV32 2
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#define GEM_CLK_DIV48 3
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#define GEM_CLK_DIV64 4
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#define GEM_CLK_DIV96 5
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/* Constants for MAN register */
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#define MACB_MAN_SOF 1
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#define MACB_MAN_WRITE 1
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#define MACB_MAN_READ 2
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#define MACB_MAN_CODE 2
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/* Bit manipulation macros */
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#define MACB_BIT(name) \
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(1 << MACB_##name##_OFFSET)
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#define MACB_BF(name,value) \
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(((value) & ((1 << MACB_##name##_SIZE) - 1)) \
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<< MACB_##name##_OFFSET)
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#define MACB_BFEXT(name,value)\
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(((value) >> MACB_##name##_OFFSET) \
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& ((1 << MACB_##name##_SIZE) - 1))
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#define MACB_BFINS(name,value,old) \
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(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
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<< MACB_##name##_OFFSET)) \
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| MACB_BF(name,value))
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#define GEM_BIT(name) \
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(1 << GEM_##name##_OFFSET)
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#define GEM_BF(name, value) \
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(((value) & ((1 << GEM_##name##_SIZE) - 1)) \
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<< GEM_##name##_OFFSET)
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#define GEM_BFEXT(name, value)\
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(((value) >> GEM_##name##_OFFSET) \
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& ((1 << GEM_##name##_SIZE) - 1))
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#define GEM_BFINS(name, value, old) \
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(((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
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<< GEM_##name##_OFFSET)) \
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| GEM_BF(name, value))
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/* Register access macros */
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#define macb_readl(port,reg) \
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__raw_readl((port)->regs + MACB_##reg)
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#define macb_writel(port,reg,value) \
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__raw_writel((value), (port)->regs + MACB_##reg)
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#define gem_readl(port, reg) \
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__raw_readl((port)->regs + GEM_##reg)
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#define gem_writel(port, reg, value) \
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__raw_writel((value), (port)->regs + GEM_##reg)
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/*
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* Conditional GEM/MACB macros. These perform the operation to the correct
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* register dependent on whether the device is a GEM or a MACB. For registers
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* and bitfields that are common across both devices, use macb_{read,write}l
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* to avoid the cost of the conditional.
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*/
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#define macb_or_gem_writel(__bp, __reg, __value) \
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({ \
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if (macb_is_gem((__bp))) \
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gem_writel((__bp), __reg, __value); \
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else \
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macb_writel((__bp), __reg, __value); \
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})
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#define macb_or_gem_readl(__bp, __reg) \
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({ \
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u32 __v; \
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if (macb_is_gem((__bp))) \
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__v = gem_readl((__bp), __reg); \
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else \
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__v = macb_readl((__bp), __reg); \
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__v; \
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})
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struct dma_desc {
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u32 addr;
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u32 ctrl;
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};
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/* DMA descriptor bitfields */
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#define MACB_RX_USED_OFFSET 0
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#define MACB_RX_USED_SIZE 1
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#define MACB_RX_WRAP_OFFSET 1
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#define MACB_RX_WRAP_SIZE 1
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#define MACB_RX_WADDR_OFFSET 2
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#define MACB_RX_WADDR_SIZE 30
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#define MACB_RX_FRMLEN_OFFSET 0
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#define MACB_RX_FRMLEN_SIZE 12
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#define MACB_RX_OFFSET_OFFSET 12
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#define MACB_RX_OFFSET_SIZE 2
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#define MACB_RX_SOF_OFFSET 14
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#define MACB_RX_SOF_SIZE 1
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#define MACB_RX_EOF_OFFSET 15
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#define MACB_RX_EOF_SIZE 1
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#define MACB_RX_CFI_OFFSET 16
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#define MACB_RX_CFI_SIZE 1
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#define MACB_RX_VLAN_PRI_OFFSET 17
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#define MACB_RX_VLAN_PRI_SIZE 3
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#define MACB_RX_PRI_TAG_OFFSET 20
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#define MACB_RX_PRI_TAG_SIZE 1
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#define MACB_RX_VLAN_TAG_OFFSET 21
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#define MACB_RX_VLAN_TAG_SIZE 1
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#define MACB_RX_TYPEID_MATCH_OFFSET 22
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#define MACB_RX_TYPEID_MATCH_SIZE 1
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#define MACB_RX_SA4_MATCH_OFFSET 23
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#define MACB_RX_SA4_MATCH_SIZE 1
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#define MACB_RX_SA3_MATCH_OFFSET 24
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#define MACB_RX_SA3_MATCH_SIZE 1
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#define MACB_RX_SA2_MATCH_OFFSET 25
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#define MACB_RX_SA2_MATCH_SIZE 1
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#define MACB_RX_SA1_MATCH_OFFSET 26
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#define MACB_RX_SA1_MATCH_SIZE 1
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#define MACB_RX_EXT_MATCH_OFFSET 28
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#define MACB_RX_EXT_MATCH_SIZE 1
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#define MACB_RX_UHASH_MATCH_OFFSET 29
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#define MACB_RX_UHASH_MATCH_SIZE 1
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#define MACB_RX_MHASH_MATCH_OFFSET 30
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#define MACB_RX_MHASH_MATCH_SIZE 1
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#define MACB_RX_BROADCAST_OFFSET 31
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#define MACB_RX_BROADCAST_SIZE 1
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#define MACB_TX_FRMLEN_OFFSET 0
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#define MACB_TX_FRMLEN_SIZE 11
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#define MACB_TX_LAST_OFFSET 15
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#define MACB_TX_LAST_SIZE 1
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#define MACB_TX_NOCRC_OFFSET 16
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#define MACB_TX_NOCRC_SIZE 1
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#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
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#define MACB_TX_BUF_EXHAUSTED_SIZE 1
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#define MACB_TX_UNDERRUN_OFFSET 28
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#define MACB_TX_UNDERRUN_SIZE 1
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#define MACB_TX_ERROR_OFFSET 29
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#define MACB_TX_ERROR_SIZE 1
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#define MACB_TX_WRAP_OFFSET 30
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#define MACB_TX_WRAP_SIZE 1
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#define MACB_TX_USED_OFFSET 31
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#define MACB_TX_USED_SIZE 1
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struct ring_info {
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struct sk_buff *skb;
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dma_addr_t mapping;
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};
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/*
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* Hardware-collected statistics. Used when updating the network
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* device stats by a periodic timer.
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*/
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struct macb_stats {
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u32 rx_pause_frames;
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u32 tx_ok;
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u32 tx_single_cols;
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u32 tx_multiple_cols;
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u32 rx_ok;
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u32 rx_fcs_errors;
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u32 rx_align_errors;
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u32 tx_deferred;
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u32 tx_late_cols;
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u32 tx_excessive_cols;
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u32 tx_underruns;
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u32 tx_carrier_errors;
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u32 rx_resource_errors;
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u32 rx_overruns;
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u32 rx_symbol_errors;
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u32 rx_oversize_pkts;
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u32 rx_jabbers;
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u32 rx_undersize_pkts;
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u32 sqe_test_errors;
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u32 rx_length_mismatch;
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u32 tx_pause_frames;
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};
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struct gem_stats {
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u32 tx_octets_31_0;
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u32 tx_octets_47_32;
|
|
u32 tx_frames;
|
|
u32 tx_broadcast_frames;
|
|
u32 tx_multicast_frames;
|
|
u32 tx_pause_frames;
|
|
u32 tx_64_byte_frames;
|
|
u32 tx_65_127_byte_frames;
|
|
u32 tx_128_255_byte_frames;
|
|
u32 tx_256_511_byte_frames;
|
|
u32 tx_512_1023_byte_frames;
|
|
u32 tx_1024_1518_byte_frames;
|
|
u32 tx_greater_than_1518_byte_frames;
|
|
u32 tx_underrun;
|
|
u32 tx_single_collision_frames;
|
|
u32 tx_multiple_collision_frames;
|
|
u32 tx_excessive_collisions;
|
|
u32 tx_late_collisions;
|
|
u32 tx_deferred_frames;
|
|
u32 tx_carrier_sense_errors;
|
|
u32 rx_octets_31_0;
|
|
u32 rx_octets_47_32;
|
|
u32 rx_frames;
|
|
u32 rx_broadcast_frames;
|
|
u32 rx_multicast_frames;
|
|
u32 rx_pause_frames;
|
|
u32 rx_64_byte_frames;
|
|
u32 rx_65_127_byte_frames;
|
|
u32 rx_128_255_byte_frames;
|
|
u32 rx_256_511_byte_frames;
|
|
u32 rx_512_1023_byte_frames;
|
|
u32 rx_1024_1518_byte_frames;
|
|
u32 rx_greater_than_1518_byte_frames;
|
|
u32 rx_undersized_frames;
|
|
u32 rx_oversize_frames;
|
|
u32 rx_jabbers;
|
|
u32 rx_frame_check_sequence_errors;
|
|
u32 rx_length_field_frame_errors;
|
|
u32 rx_symbol_errors;
|
|
u32 rx_alignment_errors;
|
|
u32 rx_resource_errors;
|
|
u32 rx_overruns;
|
|
u32 rx_ip_header_checksum_errors;
|
|
u32 rx_tcp_checksum_errors;
|
|
u32 rx_udp_checksum_errors;
|
|
};
|
|
|
|
struct macb {
|
|
void __iomem *regs;
|
|
|
|
unsigned int rx_tail;
|
|
struct dma_desc *rx_ring;
|
|
void *rx_buffers;
|
|
|
|
unsigned int tx_head, tx_tail;
|
|
struct dma_desc *tx_ring;
|
|
struct ring_info *tx_skb;
|
|
|
|
spinlock_t lock;
|
|
struct platform_device *pdev;
|
|
struct clk *pclk;
|
|
struct clk *hclk;
|
|
struct net_device *dev;
|
|
struct napi_struct napi;
|
|
struct net_device_stats stats;
|
|
union {
|
|
struct macb_stats macb;
|
|
struct gem_stats gem;
|
|
} hw_stats;
|
|
|
|
dma_addr_t rx_ring_dma;
|
|
dma_addr_t tx_ring_dma;
|
|
dma_addr_t rx_buffers_dma;
|
|
|
|
unsigned int rx_pending, tx_pending;
|
|
|
|
struct mii_bus *mii_bus;
|
|
struct phy_device *phy_dev;
|
|
unsigned int link;
|
|
unsigned int speed;
|
|
unsigned int duplex;
|
|
|
|
phy_interface_t phy_interface;
|
|
};
|
|
|
|
static inline bool macb_is_gem(struct macb *bp)
|
|
{
|
|
return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;
|
|
}
|
|
|
|
#endif /* _MACB_H */
|