5636919b5c
Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
30 lines
812 B
C
30 lines
812 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 by Waldorf Electronics
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* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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*/
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#ifndef _ASM_DELAY_H
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#define _ASM_DELAY_H
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extern void __delay(unsigned int loops);
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extern void __ndelay(unsigned int ns);
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extern void __udelay(unsigned int us);
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#define ndelay(ns) __udelay(ns)
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#define udelay(us) __udelay(us)
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/* make sure "usecs *= ..." in udelay do not overflow. */
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#if HZ >= 1000
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#define MAX_UDELAY_MS 1
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#elif HZ <= 200
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#define MAX_UDELAY_MS 5
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#else
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#define MAX_UDELAY_MS (1000 / HZ)
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#endif
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#endif /* _ASM_DELAY_H */
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