2fe2abf896
Previously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources forwarded to a bus by its upstream bridge. We've increased this size several times when the table overflowed. But there's no good limit on the number of resources because host bridges and subtractive decode bridges can forward any number of ranges to their secondary buses. This patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries, which corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4) bridge can positively decode. Any additional resources, e.g., PCI host bridge windows or subtractively-decoded regions, are kept in a list. I'd prefer a single list rather than this split table/list approach, but that requires simultaneous changes to every architecture. This approach only requires immediate changes where we set up (a) host bridges with more than four windows and (b) subtractive-decode P2P bridges, and we can incrementally change other architectures to use the list. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
26 lines
625 B
C
26 lines
625 B
C
#ifdef CONFIG_X86_64
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/*
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* sub bus (transparent) will use entres from 3 to store extra from
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* root, so need to make sure we have enough slot there.
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*/
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#define RES_NUM 16
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struct pci_root_info {
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char name[12];
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unsigned int res_num;
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struct resource res[RES_NUM];
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int bus_min;
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int bus_max;
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int node;
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int link;
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};
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/* 4 at this time, it may become to 32 */
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#define PCI_ROOT_NR 4
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extern int pci_root_num;
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extern struct pci_root_info pci_root_info[PCI_ROOT_NR];
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extern int found_all_numa_early;
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extern void update_res(struct pci_root_info *info, size_t start,
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size_t end, unsigned long flags, int merge);
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#endif
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