e360adbe29
Provide a mechanism that allows running code in IRQ context. It is most useful for NMI code that needs to interact with the rest of the system -- like wakeup a task to drain buffers. Perf currently has such a mechanism, so extract that and provide it as a generic feature, independent of perf so that others may also benefit. The IRQ context callback is generated through self-IPIs where possible, or on architectures like powerpc the decrementer (the built-in timer facility) is set to generate an interrupt immediately. Architectures that don't have anything like this get to do with a callback from the timer tick. These architectures can call irq_work_run() at the tail of any IRQ handlers that might enqueue such work (like the perf IRQ handler) to avoid undue latencies in processing the work. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Kyle McMartin <kyle@mcmartin.ca> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [ various fixes ] Signed-off-by: Huang Ying <ying.huang@intel.com> LKML-Reference: <1287036094.7768.291.camel@yhuang-dev> Signed-off-by: Ingo Molnar <mingo@elte.hu>
29 lines
758 B
C
29 lines
758 B
C
#ifndef __ASM_SH_PERF_EVENT_H
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#define __ASM_SH_PERF_EVENT_H
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struct hw_perf_event;
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#define MAX_HWEVENTS 2
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struct sh_pmu {
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const char *name;
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unsigned int num_events;
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void (*disable_all)(void);
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void (*enable_all)(void);
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void (*enable)(struct hw_perf_event *, int);
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void (*disable)(struct hw_perf_event *, int);
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u64 (*read)(int);
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int (*event_map)(int);
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unsigned int max_events;
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unsigned long raw_event_mask;
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const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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};
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/* arch/sh/kernel/perf_event.c */
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extern int register_sh_pmu(struct sh_pmu *);
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extern int reserve_pmc_hardware(void);
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extern void release_pmc_hardware(void);
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#endif /* __ASM_SH_PERF_EVENT_H */
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