72246da40f
The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
25 lines
656 B
Text
25 lines
656 B
Text
config USB_DWC3
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tristate "DesignWare USB3 DRD Core Support"
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depends on (USB || USB_GADGET)
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select USB_OTG_UTILS
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help
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Say Y or M here if your system has a Dual Role SuperSpeed
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USB controller based on the DesignWare USB3 IP Core.
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If you choose to build this driver is a dynamically linked
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module, the module will be called dwc3.ko.
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if USB_DWC3
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config USB_DWC3_DEBUG
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bool "Enable Debugging Messages"
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help
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Say Y here to enable debugging messages on DWC3 Driver.
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config USB_DWC3_VERBOSE
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bool "Enable Verbose Debugging Messages"
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depends on USB_DWC3_DEBUG
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help
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Say Y here to enable verbose debugging messages on DWC3 Driver.
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endif
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