a5715d6dfc
This allows any secondary CPU thread also to become boot cpu for POWER5. The patch is required to solve kdump boot issue when the kdump kernel is booted with parameter "maxcpus=1". XICS init code tries to match the current boot cpu id with "reg" property in each CPU node in the device tree. But CPU node is created only for primary thread CPU ids and "reg" property only reflects primary CPU ids. So when a kernel is booted on a secondary cpu thread above condition will never meet and the default distribution server is left as zero. This leads to route the interrupts to CPU 0, but which is not online at this time. We use ibm,ppc-interrupt-server#s to check for both primary and secondary CPU ids. Accordingly default distribution server value is initialized from "ibm,ppc-interrupt-gserver#s" property. We loop through ibm,ppc-interrupt-gserver#s property to find the global distribution server from the last entry that matches with boot cpuid. Signed-off-by: Mohan Kumar M <mohan@in.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
883 lines
20 KiB
C
883 lines
20 KiB
C
/*
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* arch/powerpc/platforms/pseries/xics.c
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*
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* Copyright 2000 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/signal.h>
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#include <linux/init.h>
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#include <linux/gfp.h>
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#include <linux/radix-tree.h>
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#include <linux/cpu.h>
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#include <asm/firmware.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/rtas.h>
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#include <asm/hvcall.h>
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#include <asm/machdep.h>
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#include <asm/i8259.h>
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#include "xics.h"
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#include "plpar_wrappers.h"
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#define XICS_IPI 2
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#define XICS_IRQ_SPURIOUS 0
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/* Want a priority other than 0. Various HW issues require this. */
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#define DEFAULT_PRIORITY 5
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/*
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* Mark IPIs as higher priority so we can take them inside interrupts that
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* arent marked IRQF_DISABLED
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*/
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#define IPI_PRIORITY 4
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struct xics_ipl {
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union {
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u32 word;
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u8 bytes[4];
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} xirr_poll;
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union {
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u32 word;
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u8 bytes[4];
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} xirr;
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u32 dummy;
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union {
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u32 word;
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u8 bytes[4];
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} qirr;
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};
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static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
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static unsigned int default_server = 0xFF;
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static unsigned int default_distrib_server = 0;
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static unsigned int interrupt_server_size = 8;
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static struct irq_host *xics_host;
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/*
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* XICS only has a single IPI, so encode the messages per CPU
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*/
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struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
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/* RTAS service tokens */
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static int ibm_get_xive;
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static int ibm_set_xive;
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static int ibm_int_on;
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static int ibm_int_off;
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/* Direct HW low level accessors */
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static inline unsigned int direct_xirr_info_get(int n_cpu)
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{
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return in_be32(&xics_per_cpu[n_cpu]->xirr.word);
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}
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static inline void direct_xirr_info_set(int n_cpu, int value)
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{
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out_be32(&xics_per_cpu[n_cpu]->xirr.word, value);
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}
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static inline void direct_cppr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value);
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}
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static inline void direct_qirr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
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}
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/* LPAR low level accessors */
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static inline unsigned int lpar_xirr_info_get(int n_cpu)
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{
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unsigned long lpar_rc;
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unsigned long return_value;
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lpar_rc = plpar_xirr(&return_value);
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if (lpar_rc != H_SUCCESS)
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panic(" bad return code xirr - rc = %lx \n", lpar_rc);
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return (unsigned int)return_value;
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}
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static inline void lpar_xirr_info_set(int n_cpu, int value)
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{
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unsigned long lpar_rc;
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unsigned long val64 = value & 0xffffffff;
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lpar_rc = plpar_eoi(val64);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
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val64);
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}
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static inline void lpar_cppr_info(int n_cpu, u8 value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_cppr(value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code cppr - rc = %lx\n", lpar_rc);
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}
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static inline void lpar_qirr_info(int n_cpu , u8 value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code qirr - rc = %lx\n", lpar_rc);
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}
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/* High level handlers and init code */
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#ifdef CONFIG_SMP
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static int get_irq_server(unsigned int virq)
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{
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unsigned int server;
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/* For the moment only implement delivery to all cpus or one cpu */
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cpumask_t cpumask = irq_desc[virq].affinity;
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cpumask_t tmp = CPU_MASK_NONE;
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if (!distribute_irqs)
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return default_server;
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if (cpus_equal(cpumask, CPU_MASK_ALL)) {
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server = default_distrib_server;
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} else {
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cpus_and(tmp, cpu_online_map, cpumask);
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if (cpus_empty(tmp))
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server = default_distrib_server;
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else
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server = get_hard_smp_processor_id(first_cpu(tmp));
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}
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return server;
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}
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#else
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static int get_irq_server(unsigned int virq)
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{
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return default_server;
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}
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#endif
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static void xics_unmask_irq(unsigned int virq)
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{
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unsigned int irq;
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int call_status;
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unsigned int server;
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pr_debug("xics: unmask virq %d\n", virq);
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irq = (unsigned int)irq_map[virq].hwirq;
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pr_debug(" -> map to hwirq 0x%x\n", irq);
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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return;
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server = get_irq_server(virq);
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
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DEFAULT_PRIORITY);
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if (call_status != 0) {
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printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
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"returned %d\n", irq, call_status);
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printk("set_xive %x, server %x\n", ibm_set_xive, server);
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return;
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}
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/* Now unmask the interrupt (often a no-op) */
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call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
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if (call_status != 0) {
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printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
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"returned %d\n", irq, call_status);
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return;
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}
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}
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static void xics_mask_real_irq(unsigned int irq)
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{
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int call_status;
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unsigned int server;
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if (irq == XICS_IPI)
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return;
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call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
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if (call_status != 0) {
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printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
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"ibm_int_off returned %d\n", irq, call_status);
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return;
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}
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server = get_irq_server(irq);
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/* Have to set XIVE to 0xff to be able to remove a slot */
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, 0xff);
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if (call_status != 0) {
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printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
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" returned %d\n", irq, call_status);
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return;
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}
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}
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static void xics_mask_irq(unsigned int virq)
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{
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unsigned int irq;
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pr_debug("xics: mask virq %d\n", virq);
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irq = (unsigned int)irq_map[virq].hwirq;
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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return;
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xics_mask_real_irq(irq);
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}
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static unsigned int xics_startup(unsigned int virq)
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{
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unsigned int irq;
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/* force a reverse mapping of the interrupt so it gets in the cache */
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irq = (unsigned int)irq_map[virq].hwirq;
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irq_radix_revmap(xics_host, irq);
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/* unmask it */
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xics_unmask_irq(virq);
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return 0;
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}
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static void xics_eoi_direct(unsigned int virq)
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{
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int cpu = smp_processor_id();
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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direct_xirr_info_set(cpu, (0xff << 24) | irq);
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}
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static void xics_eoi_lpar(unsigned int virq)
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{
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int cpu = smp_processor_id();
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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lpar_xirr_info_set(cpu, (0xff << 24) | irq);
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}
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static inline unsigned int xics_remap_irq(unsigned int vec)
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{
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unsigned int irq;
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vec &= 0x00ffffff;
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if (vec == XICS_IRQ_SPURIOUS)
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return NO_IRQ;
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irq = irq_radix_revmap(xics_host, vec);
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if (likely(irq != NO_IRQ))
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return irq;
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printk(KERN_ERR "Interrupt %u (real) is invalid,"
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" disabling it.\n", vec);
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xics_mask_real_irq(vec);
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return NO_IRQ;
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}
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static unsigned int xics_get_irq_direct(void)
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{
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unsigned int cpu = smp_processor_id();
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return xics_remap_irq(direct_xirr_info_get(cpu));
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}
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static unsigned int xics_get_irq_lpar(void)
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{
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unsigned int cpu = smp_processor_id();
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return xics_remap_irq(lpar_xirr_info_get(cpu));
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}
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#ifdef CONFIG_SMP
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static irqreturn_t xics_ipi_dispatch(int cpu)
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{
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WARN_ON(cpu_is_offline(cpu));
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while (xics_ipi_message[cpu].value) {
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if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNCTION);
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}
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if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_RESCHEDULE);
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}
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#if 0
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if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_MIGRATE_TASK);
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}
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#endif
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#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
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if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
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}
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#endif
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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direct_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu);
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}
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static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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lpar_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu);
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}
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void xics_cause_IPI(int cpu)
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{
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_qirr_info(cpu, IPI_PRIORITY);
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else
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direct_qirr_info(cpu, IPI_PRIORITY);
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}
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#endif /* CONFIG_SMP */
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static void xics_set_cpu_priority(int cpu, unsigned char cppr)
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{
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_cppr_info(cpu, cppr);
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else
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direct_cppr_info(cpu, cppr);
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iosync();
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}
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static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
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{
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unsigned int irq;
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int status;
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int xics_status[2];
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unsigned long newmask;
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cpumask_t tmp = CPU_MASK_NONE;
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irq = (unsigned int)irq_map[virq].hwirq;
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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return;
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status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
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if (status) {
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printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
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"returns %d\n", irq, status);
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return;
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}
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/* For the moment only implement delivery to all cpus or one cpu */
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if (cpus_equal(cpumask, CPU_MASK_ALL)) {
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newmask = default_distrib_server;
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} else {
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cpus_and(tmp, cpu_online_map, cpumask);
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if (cpus_empty(tmp))
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return;
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newmask = get_hard_smp_processor_id(first_cpu(tmp));
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}
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status = rtas_call(ibm_set_xive, 3, 1, NULL,
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irq, newmask, xics_status[1]);
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if (status) {
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printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
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"returns %d\n", irq, status);
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return;
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}
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}
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void xics_setup_cpu(void)
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{
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int cpu = smp_processor_id();
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xics_set_cpu_priority(cpu, 0xff);
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/*
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* Put the calling processor into the GIQ. This is really only
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* necessary from a secondary thread as the OF start-cpu interface
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* performs this function for us on primary threads.
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*
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* XXX: undo of teardown on kexec needs this too, as may hotplug
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*/
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rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
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(1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
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}
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static struct irq_chip xics_pic_direct = {
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.typename = " XICS ",
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.startup = xics_startup,
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.mask = xics_mask_irq,
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.unmask = xics_unmask_irq,
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.eoi = xics_eoi_direct,
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.set_affinity = xics_set_affinity
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};
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static struct irq_chip xics_pic_lpar = {
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.typename = " XICS ",
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.startup = xics_startup,
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.mask = xics_mask_irq,
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.unmask = xics_unmask_irq,
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.eoi = xics_eoi_lpar,
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.set_affinity = xics_set_affinity
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};
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static int xics_host_match(struct irq_host *h, struct device_node *node)
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{
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/* IBM machines have interrupt parents of various funky types for things
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* like vdevices, events, etc... The trick we use here is to match
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* everything here except the legacy 8259 which is compatible "chrp,iic"
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*/
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return !device_is_compatible(node, "chrp,iic");
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}
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static int xics_host_map_direct(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq);
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return 0;
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}
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static int xics_host_map_lpar(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq);
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return 0;
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}
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static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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|
/* Current xics implementation translates everything
|
|
* to level. It is not technically right for MSIs but this
|
|
* is irrelevant at this point. We might get smarter in the future
|
|
*/
|
|
*out_hwirq = intspec[0];
|
|
*out_flags = IRQ_TYPE_LEVEL_LOW;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_host_ops xics_host_direct_ops = {
|
|
.match = xics_host_match,
|
|
.map = xics_host_map_direct,
|
|
.xlate = xics_host_xlate,
|
|
};
|
|
|
|
static struct irq_host_ops xics_host_lpar_ops = {
|
|
.match = xics_host_match,
|
|
.map = xics_host_map_lpar,
|
|
.xlate = xics_host_xlate,
|
|
};
|
|
|
|
static void __init xics_init_host(void)
|
|
{
|
|
struct irq_host_ops *ops;
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
ops = &xics_host_lpar_ops;
|
|
else
|
|
ops = &xics_host_direct_ops;
|
|
xics_host = irq_alloc_host(IRQ_HOST_MAP_TREE, 0, ops,
|
|
XICS_IRQ_SPURIOUS);
|
|
BUG_ON(xics_host == NULL);
|
|
irq_set_default_host(xics_host);
|
|
}
|
|
|
|
static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
|
|
unsigned long size)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
int i;
|
|
|
|
/* This may look gross but it's good enough for now, we don't quite
|
|
* have a hard -> linux processor id matching.
|
|
*/
|
|
for_each_possible_cpu(i) {
|
|
if (!cpu_present(i))
|
|
continue;
|
|
if (hw_id == get_hard_smp_processor_id(i)) {
|
|
xics_per_cpu[i] = ioremap(addr, size);
|
|
return;
|
|
}
|
|
}
|
|
#else
|
|
if (hw_id != 0)
|
|
return;
|
|
xics_per_cpu[0] = ioremap(addr, size);
|
|
#endif /* CONFIG_SMP */
|
|
}
|
|
|
|
static void __init xics_init_one_node(struct device_node *np,
|
|
unsigned int *indx)
|
|
{
|
|
unsigned int ilen;
|
|
const u32 *ireg;
|
|
|
|
/* This code does the theorically broken assumption that the interrupt
|
|
* server numbers are the same as the hard CPU numbers.
|
|
* This happens to be the case so far but we are playing with fire...
|
|
* should be fixed one of these days. -BenH.
|
|
*/
|
|
ireg = get_property(np, "ibm,interrupt-server-ranges", NULL);
|
|
|
|
/* Do that ever happen ? we'll know soon enough... but even good'old
|
|
* f80 does have that property ..
|
|
*/
|
|
WARN_ON(ireg == NULL);
|
|
if (ireg) {
|
|
/*
|
|
* set node starting index for this node
|
|
*/
|
|
*indx = *ireg;
|
|
}
|
|
ireg = get_property(np, "reg", &ilen);
|
|
if (!ireg)
|
|
panic("xics_init_IRQ: can't find interrupt reg property");
|
|
|
|
while (ilen >= (4 * sizeof(u32))) {
|
|
unsigned long addr, size;
|
|
|
|
/* XXX Use proper OF parsing code here !!! */
|
|
addr = (unsigned long)*ireg++ << 32;
|
|
ilen -= sizeof(u32);
|
|
addr |= *ireg++;
|
|
ilen -= sizeof(u32);
|
|
size = (unsigned long)*ireg++ << 32;
|
|
ilen -= sizeof(u32);
|
|
size |= *ireg++;
|
|
ilen -= sizeof(u32);
|
|
xics_map_one_cpu(*indx, addr, size);
|
|
(*indx)++;
|
|
}
|
|
}
|
|
|
|
|
|
static void __init xics_setup_8259_cascade(void)
|
|
{
|
|
struct device_node *np, *old, *found = NULL;
|
|
int cascade, naddr;
|
|
const u32 *addrp;
|
|
unsigned long intack = 0;
|
|
|
|
for_each_node_by_type(np, "interrupt-controller")
|
|
if (device_is_compatible(np, "chrp,iic")) {
|
|
found = np;
|
|
break;
|
|
}
|
|
if (found == NULL) {
|
|
printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
|
|
return;
|
|
}
|
|
cascade = irq_of_parse_and_map(found, 0);
|
|
if (cascade == NO_IRQ) {
|
|
printk(KERN_ERR "xics: failed to map cascade interrupt");
|
|
return;
|
|
}
|
|
pr_debug("xics: cascade mapped to irq %d\n", cascade);
|
|
|
|
for (old = of_node_get(found); old != NULL ; old = np) {
|
|
np = of_get_parent(old);
|
|
of_node_put(old);
|
|
if (np == NULL)
|
|
break;
|
|
if (strcmp(np->name, "pci") != 0)
|
|
continue;
|
|
addrp = get_property(np, "8259-interrupt-acknowledge", NULL);
|
|
if (addrp == NULL)
|
|
continue;
|
|
naddr = prom_n_addr_cells(np);
|
|
intack = addrp[naddr-1];
|
|
if (naddr > 1)
|
|
intack |= ((unsigned long)addrp[naddr-2]) << 32;
|
|
}
|
|
if (intack)
|
|
printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack);
|
|
i8259_init(found, intack);
|
|
of_node_put(found);
|
|
set_irq_chained_handler(cascade, pseries_8259_cascade);
|
|
}
|
|
|
|
static struct device_node *cpuid_to_of_node(int cpu)
|
|
{
|
|
struct device_node *np;
|
|
u32 hcpuid = get_hard_smp_processor_id(cpu);
|
|
|
|
for_each_node_by_type(np, "cpu") {
|
|
int i, len;
|
|
const u32 *intserv;
|
|
|
|
intserv = get_property(np, "ibm,ppc-interrupt-server#s", &len);
|
|
|
|
if (!intserv)
|
|
intserv = get_property(np, "reg", &len);
|
|
|
|
i = len / sizeof(u32);
|
|
|
|
while (i--)
|
|
if (intserv[i] == hcpuid)
|
|
return np;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
void __init xics_init_IRQ(void)
|
|
{
|
|
int i, j;
|
|
struct device_node *np;
|
|
u32 ilen, indx = 0;
|
|
const u32 *ireg, *isize;
|
|
int found = 0;
|
|
u32 hcpuid;
|
|
|
|
ppc64_boot_msg(0x20, "XICS Init");
|
|
|
|
ibm_get_xive = rtas_token("ibm,get-xive");
|
|
ibm_set_xive = rtas_token("ibm,set-xive");
|
|
ibm_int_on = rtas_token("ibm,int-on");
|
|
ibm_int_off = rtas_token("ibm,int-off");
|
|
|
|
for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
|
|
found = 1;
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
break;
|
|
xics_init_one_node(np, &indx);
|
|
}
|
|
if (found == 0)
|
|
return;
|
|
|
|
xics_init_host();
|
|
|
|
/* Find the server numbers for the boot cpu. */
|
|
np = cpuid_to_of_node(boot_cpuid);
|
|
BUG_ON(!np);
|
|
ireg = get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
|
|
if (!ireg)
|
|
goto skip_gserver_check;
|
|
i = ilen / sizeof(int);
|
|
hcpuid = get_hard_smp_processor_id(boot_cpuid);
|
|
|
|
/* Global interrupt distribution server is specified in the last
|
|
* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
|
|
* entry fom this property for current boot cpu id and use it as
|
|
* default distribution server
|
|
*/
|
|
for (j = 0; j < i; j += 2) {
|
|
if (ireg[j] == hcpuid) {
|
|
default_server = hcpuid;
|
|
default_distrib_server = ireg[j+1];
|
|
|
|
isize = get_property(np,
|
|
"ibm,interrupt-server#-size", NULL);
|
|
if (isize)
|
|
interrupt_server_size = *isize;
|
|
}
|
|
}
|
|
skip_gserver_check:
|
|
of_node_put(np);
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
ppc_md.get_irq = xics_get_irq_lpar;
|
|
else
|
|
ppc_md.get_irq = xics_get_irq_direct;
|
|
|
|
xics_setup_cpu();
|
|
|
|
xics_setup_8259_cascade();
|
|
|
|
ppc64_boot_msg(0x21, "XICS Done");
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
void xics_request_IPIs(void)
|
|
{
|
|
unsigned int ipi;
|
|
|
|
ipi = irq_create_mapping(xics_host, XICS_IPI);
|
|
BUG_ON(ipi == NO_IRQ);
|
|
|
|
/*
|
|
* IPIs are marked IRQF_DISABLED as they must run with irqs
|
|
* disabled
|
|
*/
|
|
set_irq_handler(ipi, handle_percpu_irq);
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
|
|
"IPI", NULL);
|
|
else
|
|
request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
|
|
"IPI", NULL);
|
|
}
|
|
#endif /* CONFIG_SMP */
|
|
|
|
void xics_teardown_cpu(int secondary)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
unsigned int ipi;
|
|
struct irq_desc *desc;
|
|
|
|
xics_set_cpu_priority(cpu, 0);
|
|
|
|
/*
|
|
* Clear IPI
|
|
*/
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
lpar_qirr_info(cpu, 0xff);
|
|
else
|
|
direct_qirr_info(cpu, 0xff);
|
|
|
|
/*
|
|
* we need to EOI the IPI if we got here from kexec down IPI
|
|
*
|
|
* probably need to check all the other interrupts too
|
|
* should we be flagging idle loop instead?
|
|
* or creating some task to be scheduled?
|
|
*/
|
|
|
|
ipi = irq_find_mapping(xics_host, XICS_IPI);
|
|
if (ipi == XICS_IRQ_SPURIOUS)
|
|
return;
|
|
desc = get_irq_desc(ipi);
|
|
if (desc->chip && desc->chip->eoi)
|
|
desc->chip->eoi(ipi);
|
|
|
|
/*
|
|
* Some machines need to have at least one cpu in the GIQ,
|
|
* so leave the master cpu in the group.
|
|
*/
|
|
if (secondary)
|
|
rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
|
|
(1UL << interrupt_server_size) - 1 -
|
|
default_distrib_server, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
/* Interrupts are disabled. */
|
|
void xics_migrate_irqs_away(void)
|
|
{
|
|
int status;
|
|
unsigned int irq, virq, cpu = smp_processor_id();
|
|
|
|
/* Reject any interrupt that was queued to us... */
|
|
xics_set_cpu_priority(cpu, 0);
|
|
|
|
/* remove ourselves from the global interrupt queue */
|
|
status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
|
|
(1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
|
|
WARN_ON(status < 0);
|
|
|
|
/* Allow IPIs again... */
|
|
xics_set_cpu_priority(cpu, DEFAULT_PRIORITY);
|
|
|
|
for_each_irq(virq) {
|
|
struct irq_desc *desc;
|
|
int xics_status[2];
|
|
unsigned long flags;
|
|
|
|
/* We cant set affinity on ISA interrupts */
|
|
if (virq < NUM_ISA_INTERRUPTS)
|
|
continue;
|
|
if (irq_map[virq].host != xics_host)
|
|
continue;
|
|
irq = (unsigned int)irq_map[virq].hwirq;
|
|
/* We need to get IPIs still. */
|
|
if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
|
|
continue;
|
|
desc = get_irq_desc(virq);
|
|
|
|
/* We only need to migrate enabled IRQS */
|
|
if (desc == NULL || desc->chip == NULL
|
|
|| desc->action == NULL
|
|
|| desc->chip->set_affinity == NULL)
|
|
continue;
|
|
|
|
spin_lock_irqsave(&desc->lock, flags);
|
|
|
|
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
|
|
if (status) {
|
|
printk(KERN_ERR "migrate_irqs_away: irq=%u "
|
|
"ibm,get-xive returns %d\n",
|
|
virq, status);
|
|
goto unlock;
|
|
}
|
|
|
|
/*
|
|
* We only support delivery to all cpus or to one cpu.
|
|
* The irq has to be migrated only in the single cpu
|
|
* case.
|
|
*/
|
|
if (xics_status[0] != get_hard_smp_processor_id(cpu))
|
|
goto unlock;
|
|
|
|
printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
|
|
virq, cpu);
|
|
|
|
/* Reset affinity to all cpus */
|
|
desc->chip->set_affinity(virq, CPU_MASK_ALL);
|
|
irq_desc[irq].affinity = CPU_MASK_ALL;
|
|
unlock:
|
|
spin_unlock_irqrestore(&desc->lock, flags);
|
|
}
|
|
}
|
|
#endif
|