55c9551773
In SDM450, WSA reset pin is shared for both WSA left and right speakers. When reset pin toggled, both devices enumerate and can be filled in any order in SWRM_DEV list. But get_logical_address loops only once for first slave addition and fails if the device entry is present at second in SWRM_DEV list. Update logic of get_logical_address to loop through max devices possible. CRs-Fixed: 2196399 Change-Id: Ie31cea5a9b22e09a3c5c01e177cd1b78e8d2f28d Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SWR_WCD_CTRL_H
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#define _SWR_WCD_CTRL_H
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#include <linux/module.h>
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#include <soc/swr-wcd.h>
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#define SWR_MAX_ROW 0 /* Rows = 48 */
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#define SWR_MAX_COL 7 /* Cols = 16 */
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#define SWR_MIN_COL 0 /* Cols = 2 */
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#define SWR_WCD_NAME "swr-wcd"
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#define SWR_MSTR_PORT_LEN 8 /* Number of master ports */
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#define SWR_MAX_SLAVE_DEVICES 11
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#define SWRM_VERSION_1_0 0x01010000
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#define SWRM_VERSION_1_2 0x01030000
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#define SWRM_VERSION_1_3 0x01040000
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enum {
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SWR_MSTR_PAUSE,
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SWR_MSTR_RESUME,
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SWR_MSTR_UP,
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SWR_MSTR_DOWN,
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};
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enum {
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SWR_IRQ_FREE,
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SWR_IRQ_REGISTER,
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};
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enum {
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SWR_DAC_PORT,
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SWR_COMP_PORT,
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SWR_BOOST_PORT,
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SWR_VISENSE_PORT,
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};
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struct usecase {
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u8 num_port;
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u8 num_ch;
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u32 chrate;
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};
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struct port_params {
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u8 si;
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u8 off1;
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u8 off2;
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};
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struct swrm_mports {
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struct list_head list;
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u8 id;
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};
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struct swr_ctrl_platform_data {
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void *handle; /* holds priv data */
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int (*read)(void *handle, int reg);
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int (*write)(void *handle, int reg, int val);
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int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
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int (*clk)(void *handle, bool enable);
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int (*reg_irq)(void *handle, irqreturn_t(*irq_handler)(int irq,
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void *data), void *swr_handle, int type);
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};
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struct swr_mstr_ctrl {
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struct swr_master master;
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struct device *dev;
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struct resource *supplies;
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struct clk *mclk;
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int clk_ref_count;
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struct completion reset;
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struct completion broadcast;
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struct mutex mlock;
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struct mutex reslock;
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u8 rcmd_id;
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u8 wcmd_id;
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void *handle; /* SWR Master handle from client for read and writes */
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int (*read)(void *handle, int reg);
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int (*write)(void *handle, int reg, int val);
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int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
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int (*clk)(void *handle, bool enable);
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int (*reg_irq)(void *handle, irqreturn_t(*irq_handler)(int irq,
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void *data), void *swr_handle, int type);
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int irq;
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int version;
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u32 num_dev;
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int num_enum_slaves;
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int slave_status;
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struct swr_mstr_port *mstr_port;
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struct list_head mport_list;
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int state;
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struct platform_device *pdev;
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int num_rx_chs;
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u8 num_cfg_devs;
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};
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#endif /* _SWR_WCD_CTRL_H */
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