55b8fd4f42
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
7 lines
207 B
Makefile
7 lines
207 B
Makefile
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obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
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clk-mux.o clk-divider.o clk-fixed-factor.o
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# SoCs specific
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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