148f9bb877
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0
("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/x86 uses of the __cpuinit macros from
all C files. x86 only had the one __CPUINIT used in assembly files,
and it wasn't paired off with a .previous or a __FINIT, so we can
delete it directly w/o any corresponding additional change there.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Acked-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
1247 lines
32 KiB
C
1247 lines
32 KiB
C
/*
|
|
* Routines to indentify caches on Intel CPU.
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*
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* Changes:
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* Venkatesh Pallipadi : Adding cache identification through cpuid(4)
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* Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
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* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/compiler.h>
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <asm/processor.h>
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#include <linux/smp.h>
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#include <asm/amd_nb.h>
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#include <asm/smp.h>
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#define LVL_1_INST 1
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#define LVL_1_DATA 2
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#define LVL_2 3
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#define LVL_3 4
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#define LVL_TRACE 5
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struct _cache_table {
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unsigned char descriptor;
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char cache_type;
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short size;
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};
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#define MB(x) ((x) * 1024)
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/* All the cache descriptor types we care about (no TLB or
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trace cache entries) */
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static const struct _cache_table cache_table[] =
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{
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{ 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
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{ 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
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{ 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
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{ 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
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{ 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
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{ 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
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{ 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
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{ 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
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{ 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
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{ 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
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{ 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
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{ 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
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{ 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
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{ 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
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{ 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
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{ 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
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{ 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
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{ 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
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{ 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
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{ 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
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{ 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
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{ 0x48, LVL_2, MB(3) }, /* 12-way set assoc, 64 byte line size */
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{ 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
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{ 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
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{ 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
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{ 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
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{ 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
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{ 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
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{ 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
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{ 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
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{ 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
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{ 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
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{ 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
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{ 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
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{ 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
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{ 0x80, LVL_2, 512 }, /* 8-way set assoc, 64 byte line size */
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{ 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
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{ 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
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{ 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
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{ 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
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{ 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
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{ 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
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{ 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
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{ 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
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{ 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
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{ 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
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{ 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
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{ 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
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{ 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
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{ 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
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{ 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
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{ 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
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{ 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
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{ 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
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{ 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
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{ 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
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{ 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
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{ 0x00, 0, 0}
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};
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enum _cache_type {
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CACHE_TYPE_NULL = 0,
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CACHE_TYPE_DATA = 1,
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CACHE_TYPE_INST = 2,
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CACHE_TYPE_UNIFIED = 3
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};
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union _cpuid4_leaf_eax {
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struct {
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enum _cache_type type:5;
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unsigned int level:3;
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unsigned int is_self_initializing:1;
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unsigned int is_fully_associative:1;
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unsigned int reserved:4;
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unsigned int num_threads_sharing:12;
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unsigned int num_cores_on_die:6;
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} split;
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u32 full;
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};
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union _cpuid4_leaf_ebx {
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struct {
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unsigned int coherency_line_size:12;
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unsigned int physical_line_partition:10;
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unsigned int ways_of_associativity:10;
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} split;
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u32 full;
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};
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union _cpuid4_leaf_ecx {
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struct {
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unsigned int number_of_sets:32;
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} split;
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u32 full;
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};
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struct _cpuid4_info_regs {
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned long size;
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struct amd_northbridge *nb;
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};
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struct _cpuid4_info {
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struct _cpuid4_info_regs base;
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DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
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};
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unsigned short num_cache_leaves;
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/* AMD doesn't have CPUID4. Emulate it here to report the same
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information to the user. This makes some assumptions about the machine:
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L2 not shared, no SMT etc. that is currently true on AMD CPUs.
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In theory the TLBs could be reported as fake type (they are in "dummy").
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Maybe later */
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union l1_cache {
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struct {
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unsigned line_size:8;
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unsigned lines_per_tag:8;
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unsigned assoc:8;
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unsigned size_in_kb:8;
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};
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unsigned val;
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};
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union l2_cache {
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struct {
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unsigned line_size:8;
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unsigned lines_per_tag:4;
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unsigned assoc:4;
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unsigned size_in_kb:16;
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};
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unsigned val;
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};
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union l3_cache {
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struct {
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unsigned line_size:8;
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unsigned lines_per_tag:4;
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unsigned assoc:4;
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unsigned res:2;
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unsigned size_encoded:14;
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};
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unsigned val;
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};
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static const unsigned short assocs[] = {
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[1] = 1,
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[2] = 2,
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[4] = 4,
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[6] = 8,
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[8] = 16,
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[0xa] = 32,
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[0xb] = 48,
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[0xc] = 64,
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[0xd] = 96,
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[0xe] = 128,
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[0xf] = 0xffff /* fully associative - no way to show this currently */
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};
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static const unsigned char levels[] = { 1, 1, 2, 3 };
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static const unsigned char types[] = { 1, 2, 3, 3 };
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static void
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amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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union _cpuid4_leaf_ebx *ebx,
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union _cpuid4_leaf_ecx *ecx)
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{
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unsigned dummy;
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unsigned line_size, lines_per_tag, assoc, size_in_kb;
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union l1_cache l1i, l1d;
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union l2_cache l2;
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union l3_cache l3;
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union l1_cache *l1 = &l1d;
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eax->full = 0;
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ebx->full = 0;
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ecx->full = 0;
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cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
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cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
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switch (leaf) {
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case 1:
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l1 = &l1i;
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case 0:
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if (!l1->val)
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return;
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assoc = assocs[l1->assoc];
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line_size = l1->line_size;
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lines_per_tag = l1->lines_per_tag;
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size_in_kb = l1->size_in_kb;
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break;
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case 2:
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if (!l2.val)
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return;
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assoc = assocs[l2.assoc];
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line_size = l2.line_size;
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lines_per_tag = l2.lines_per_tag;
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/* cpu_data has errata corrections for K7 applied */
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size_in_kb = __this_cpu_read(cpu_info.x86_cache_size);
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break;
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case 3:
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if (!l3.val)
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return;
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assoc = assocs[l3.assoc];
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line_size = l3.line_size;
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lines_per_tag = l3.lines_per_tag;
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size_in_kb = l3.size_encoded * 512;
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if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
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size_in_kb = size_in_kb >> 1;
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assoc = assoc >> 1;
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}
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break;
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default:
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return;
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}
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eax->split.is_self_initializing = 1;
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eax->split.type = types[leaf];
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eax->split.level = levels[leaf];
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eax->split.num_threads_sharing = 0;
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eax->split.num_cores_on_die = __this_cpu_read(cpu_info.x86_max_cores) - 1;
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|
|
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if (assoc == 0xffff)
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eax->split.is_fully_associative = 1;
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ebx->split.coherency_line_size = line_size - 1;
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ebx->split.ways_of_associativity = assoc - 1;
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ebx->split.physical_line_partition = lines_per_tag - 1;
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ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
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(ebx->split.ways_of_associativity + 1) - 1;
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}
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struct _cache_attr {
|
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count,
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unsigned int);
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};
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|
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#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)
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/*
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* L3 cache descriptors
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*/
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static void amd_calc_l3_indices(struct amd_northbridge *nb)
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{
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struct amd_l3_cache *l3 = &nb->l3_cache;
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unsigned int sc0, sc1, sc2, sc3;
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u32 val = 0;
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pci_read_config_dword(nb->misc, 0x1C4, &val);
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|
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/* calculate subcache sizes */
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l3->subcaches[0] = sc0 = !(val & BIT(0));
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l3->subcaches[1] = sc1 = !(val & BIT(4));
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|
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if (boot_cpu_data.x86 == 0x15) {
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l3->subcaches[0] = sc0 += !(val & BIT(1));
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|
l3->subcaches[1] = sc1 += !(val & BIT(5));
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}
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|
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l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9));
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l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
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|
|
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l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
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}
|
|
|
|
static void amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
|
|
{
|
|
int node;
|
|
|
|
/* only for L3, and not in virtualized environments */
|
|
if (index < 3)
|
|
return;
|
|
|
|
node = amd_get_nb_id(smp_processor_id());
|
|
this_leaf->nb = node_to_amd_nb(node);
|
|
if (this_leaf->nb && !this_leaf->nb->l3_cache.indices)
|
|
amd_calc_l3_indices(this_leaf->nb);
|
|
}
|
|
|
|
/*
|
|
* check whether a slot used for disabling an L3 index is occupied.
|
|
* @l3: L3 cache descriptor
|
|
* @slot: slot number (0..1)
|
|
*
|
|
* @returns: the disabled index if used or negative value if slot free.
|
|
*/
|
|
int amd_get_l3_disable_slot(struct amd_northbridge *nb, unsigned slot)
|
|
{
|
|
unsigned int reg = 0;
|
|
|
|
pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®);
|
|
|
|
/* check whether this slot is activated already */
|
|
if (reg & (3UL << 30))
|
|
return reg & 0xfff;
|
|
|
|
return -1;
|
|
}
|
|
|
|
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
|
|
unsigned int slot)
|
|
{
|
|
int index;
|
|
|
|
if (!this_leaf->base.nb || !amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
|
|
return -EINVAL;
|
|
|
|
index = amd_get_l3_disable_slot(this_leaf->base.nb, slot);
|
|
if (index >= 0)
|
|
return sprintf(buf, "%d\n", index);
|
|
|
|
return sprintf(buf, "FREE\n");
|
|
}
|
|
|
|
#define SHOW_CACHE_DISABLE(slot) \
|
|
static ssize_t \
|
|
show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \
|
|
unsigned int cpu) \
|
|
{ \
|
|
return show_cache_disable(this_leaf, buf, slot); \
|
|
}
|
|
SHOW_CACHE_DISABLE(0)
|
|
SHOW_CACHE_DISABLE(1)
|
|
|
|
static void amd_l3_disable_index(struct amd_northbridge *nb, int cpu,
|
|
unsigned slot, unsigned long idx)
|
|
{
|
|
int i;
|
|
|
|
idx |= BIT(30);
|
|
|
|
/*
|
|
* disable index in all 4 subcaches
|
|
*/
|
|
for (i = 0; i < 4; i++) {
|
|
u32 reg = idx | (i << 20);
|
|
|
|
if (!nb->l3_cache.subcaches[i])
|
|
continue;
|
|
|
|
pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);
|
|
|
|
/*
|
|
* We need to WBINVD on a core on the node containing the L3
|
|
* cache which indices we disable therefore a simple wbinvd()
|
|
* is not sufficient.
|
|
*/
|
|
wbinvd_on_cpu(cpu);
|
|
|
|
reg |= BIT(31);
|
|
pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* disable a L3 cache index by using a disable-slot
|
|
*
|
|
* @l3: L3 cache descriptor
|
|
* @cpu: A CPU on the node containing the L3 cache
|
|
* @slot: slot number (0..1)
|
|
* @index: index to disable
|
|
*
|
|
* @return: 0 on success, error status on failure
|
|
*/
|
|
int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
|
|
unsigned long index)
|
|
{
|
|
int ret = 0;
|
|
|
|
/* check if @slot is already used or the index is already disabled */
|
|
ret = amd_get_l3_disable_slot(nb, slot);
|
|
if (ret >= 0)
|
|
return -EEXIST;
|
|
|
|
if (index > nb->l3_cache.indices)
|
|
return -EINVAL;
|
|
|
|
/* check whether the other slot has disabled the same index already */
|
|
if (index == amd_get_l3_disable_slot(nb, !slot))
|
|
return -EEXIST;
|
|
|
|
amd_l3_disable_index(nb, cpu, slot, index);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
|
|
const char *buf, size_t count,
|
|
unsigned int slot)
|
|
{
|
|
unsigned long val = 0;
|
|
int cpu, err = 0;
|
|
|
|
if (!capable(CAP_SYS_ADMIN))
|
|
return -EPERM;
|
|
|
|
if (!this_leaf->base.nb || !amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
|
|
return -EINVAL;
|
|
|
|
cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
|
|
|
|
if (strict_strtoul(buf, 10, &val) < 0)
|
|
return -EINVAL;
|
|
|
|
err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
|
|
if (err) {
|
|
if (err == -EEXIST)
|
|
pr_warning("L3 slot %d in use/index already disabled!\n",
|
|
slot);
|
|
return err;
|
|
}
|
|
return count;
|
|
}
|
|
|
|
#define STORE_CACHE_DISABLE(slot) \
|
|
static ssize_t \
|
|
store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \
|
|
const char *buf, size_t count, \
|
|
unsigned int cpu) \
|
|
{ \
|
|
return store_cache_disable(this_leaf, buf, count, slot); \
|
|
}
|
|
STORE_CACHE_DISABLE(0)
|
|
STORE_CACHE_DISABLE(1)
|
|
|
|
static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
|
|
show_cache_disable_0, store_cache_disable_0);
|
|
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
|
|
show_cache_disable_1, store_cache_disable_1);
|
|
|
|
static ssize_t
|
|
show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu)
|
|
{
|
|
if (!this_leaf->base.nb || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
|
return -EINVAL;
|
|
|
|
return sprintf(buf, "%x\n", amd_get_subcaches(cpu));
|
|
}
|
|
|
|
static ssize_t
|
|
store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count,
|
|
unsigned int cpu)
|
|
{
|
|
unsigned long val;
|
|
|
|
if (!capable(CAP_SYS_ADMIN))
|
|
return -EPERM;
|
|
|
|
if (!this_leaf->base.nb || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
|
return -EINVAL;
|
|
|
|
if (strict_strtoul(buf, 16, &val) < 0)
|
|
return -EINVAL;
|
|
|
|
if (amd_set_subcaches(cpu, val))
|
|
return -EINVAL;
|
|
|
|
return count;
|
|
}
|
|
|
|
static struct _cache_attr subcaches =
|
|
__ATTR(subcaches, 0644, show_subcaches, store_subcaches);
|
|
|
|
#else
|
|
#define amd_init_l3_cache(x, y)
|
|
#endif /* CONFIG_AMD_NB && CONFIG_SYSFS */
|
|
|
|
static int
|
|
cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf)
|
|
{
|
|
union _cpuid4_leaf_eax eax;
|
|
union _cpuid4_leaf_ebx ebx;
|
|
union _cpuid4_leaf_ecx ecx;
|
|
unsigned edx;
|
|
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
|
|
if (cpu_has_topoext)
|
|
cpuid_count(0x8000001d, index, &eax.full,
|
|
&ebx.full, &ecx.full, &edx);
|
|
else
|
|
amd_cpuid4(index, &eax, &ebx, &ecx);
|
|
amd_init_l3_cache(this_leaf, index);
|
|
} else {
|
|
cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
|
|
}
|
|
|
|
if (eax.split.type == CACHE_TYPE_NULL)
|
|
return -EIO; /* better error ? */
|
|
|
|
this_leaf->eax = eax;
|
|
this_leaf->ebx = ebx;
|
|
this_leaf->ecx = ecx;
|
|
this_leaf->size = (ecx.split.number_of_sets + 1) *
|
|
(ebx.split.coherency_line_size + 1) *
|
|
(ebx.split.physical_line_partition + 1) *
|
|
(ebx.split.ways_of_associativity + 1);
|
|
return 0;
|
|
}
|
|
|
|
static int find_num_cache_leaves(struct cpuinfo_x86 *c)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx, op;
|
|
union _cpuid4_leaf_eax cache_eax;
|
|
int i = -1;
|
|
|
|
if (c->x86_vendor == X86_VENDOR_AMD)
|
|
op = 0x8000001d;
|
|
else
|
|
op = 4;
|
|
|
|
do {
|
|
++i;
|
|
/* Do cpuid(op) loop to find out num_cache_leaves */
|
|
cpuid_count(op, i, &eax, &ebx, &ecx, &edx);
|
|
cache_eax.full = eax;
|
|
} while (cache_eax.split.type != CACHE_TYPE_NULL);
|
|
return i;
|
|
}
|
|
|
|
void init_amd_cacheinfo(struct cpuinfo_x86 *c)
|
|
{
|
|
|
|
if (cpu_has_topoext) {
|
|
num_cache_leaves = find_num_cache_leaves(c);
|
|
} else if (c->extended_cpuid_level >= 0x80000006) {
|
|
if (cpuid_edx(0x80000006) & 0xf000)
|
|
num_cache_leaves = 4;
|
|
else
|
|
num_cache_leaves = 3;
|
|
}
|
|
}
|
|
|
|
unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
|
|
{
|
|
/* Cache sizes */
|
|
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
|
|
unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
|
|
unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
|
|
unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
|
|
#ifdef CONFIG_X86_HT
|
|
unsigned int cpu = c->cpu_index;
|
|
#endif
|
|
|
|
if (c->cpuid_level > 3) {
|
|
static int is_initialized;
|
|
|
|
if (is_initialized == 0) {
|
|
/* Init num_cache_leaves from boot CPU */
|
|
num_cache_leaves = find_num_cache_leaves(c);
|
|
is_initialized++;
|
|
}
|
|
|
|
/*
|
|
* Whenever possible use cpuid(4), deterministic cache
|
|
* parameters cpuid leaf to find the cache details
|
|
*/
|
|
for (i = 0; i < num_cache_leaves; i++) {
|
|
struct _cpuid4_info_regs this_leaf = {};
|
|
int retval;
|
|
|
|
retval = cpuid4_cache_lookup_regs(i, &this_leaf);
|
|
if (retval < 0)
|
|
continue;
|
|
|
|
switch (this_leaf.eax.split.level) {
|
|
case 1:
|
|
if (this_leaf.eax.split.type == CACHE_TYPE_DATA)
|
|
new_l1d = this_leaf.size/1024;
|
|
else if (this_leaf.eax.split.type == CACHE_TYPE_INST)
|
|
new_l1i = this_leaf.size/1024;
|
|
break;
|
|
case 2:
|
|
new_l2 = this_leaf.size/1024;
|
|
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
|
|
index_msb = get_count_order(num_threads_sharing);
|
|
l2_id = c->apicid & ~((1 << index_msb) - 1);
|
|
break;
|
|
case 3:
|
|
new_l3 = this_leaf.size/1024;
|
|
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
|
|
index_msb = get_count_order(num_threads_sharing);
|
|
l3_id = c->apicid & ~((1 << index_msb) - 1);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
/*
|
|
* Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
|
|
* trace cache
|
|
*/
|
|
if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
|
|
/* supports eax=2 call */
|
|
int j, n;
|
|
unsigned int regs[4];
|
|
unsigned char *dp = (unsigned char *)regs;
|
|
int only_trace = 0;
|
|
|
|
if (num_cache_leaves != 0 && c->x86 == 15)
|
|
only_trace = 1;
|
|
|
|
/* Number of times to iterate */
|
|
n = cpuid_eax(2) & 0xFF;
|
|
|
|
for (i = 0 ; i < n ; i++) {
|
|
cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
|
|
|
|
/* If bit 31 is set, this is an unknown format */
|
|
for (j = 0 ; j < 3 ; j++)
|
|
if (regs[j] & (1 << 31))
|
|
regs[j] = 0;
|
|
|
|
/* Byte 0 is level count, not a descriptor */
|
|
for (j = 1 ; j < 16 ; j++) {
|
|
unsigned char des = dp[j];
|
|
unsigned char k = 0;
|
|
|
|
/* look up this descriptor in the table */
|
|
while (cache_table[k].descriptor != 0) {
|
|
if (cache_table[k].descriptor == des) {
|
|
if (only_trace && cache_table[k].cache_type != LVL_TRACE)
|
|
break;
|
|
switch (cache_table[k].cache_type) {
|
|
case LVL_1_INST:
|
|
l1i += cache_table[k].size;
|
|
break;
|
|
case LVL_1_DATA:
|
|
l1d += cache_table[k].size;
|
|
break;
|
|
case LVL_2:
|
|
l2 += cache_table[k].size;
|
|
break;
|
|
case LVL_3:
|
|
l3 += cache_table[k].size;
|
|
break;
|
|
case LVL_TRACE:
|
|
trace += cache_table[k].size;
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
k++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (new_l1d)
|
|
l1d = new_l1d;
|
|
|
|
if (new_l1i)
|
|
l1i = new_l1i;
|
|
|
|
if (new_l2) {
|
|
l2 = new_l2;
|
|
#ifdef CONFIG_X86_HT
|
|
per_cpu(cpu_llc_id, cpu) = l2_id;
|
|
#endif
|
|
}
|
|
|
|
if (new_l3) {
|
|
l3 = new_l3;
|
|
#ifdef CONFIG_X86_HT
|
|
per_cpu(cpu_llc_id, cpu) = l3_id;
|
|
#endif
|
|
}
|
|
|
|
c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
|
|
|
|
return l2;
|
|
}
|
|
|
|
#ifdef CONFIG_SYSFS
|
|
|
|
/* pointer to _cpuid4_info array (for each cache leaf) */
|
|
static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
|
|
#define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static int cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
|
|
{
|
|
struct _cpuid4_info *this_leaf;
|
|
int i, sibling;
|
|
|
|
if (cpu_has_topoext) {
|
|
unsigned int apicid, nshared, first, last;
|
|
|
|
if (!per_cpu(ici_cpuid4_info, cpu))
|
|
return 0;
|
|
|
|
this_leaf = CPUID4_INFO_IDX(cpu, index);
|
|
nshared = this_leaf->base.eax.split.num_threads_sharing + 1;
|
|
apicid = cpu_data(cpu).apicid;
|
|
first = apicid - (apicid % nshared);
|
|
last = first + nshared - 1;
|
|
|
|
for_each_online_cpu(i) {
|
|
apicid = cpu_data(i).apicid;
|
|
if ((apicid < first) || (apicid > last))
|
|
continue;
|
|
if (!per_cpu(ici_cpuid4_info, i))
|
|
continue;
|
|
this_leaf = CPUID4_INFO_IDX(i, index);
|
|
|
|
for_each_online_cpu(sibling) {
|
|
apicid = cpu_data(sibling).apicid;
|
|
if ((apicid < first) || (apicid > last))
|
|
continue;
|
|
set_bit(sibling, this_leaf->shared_cpu_map);
|
|
}
|
|
}
|
|
} else if (index == 3) {
|
|
for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
|
|
if (!per_cpu(ici_cpuid4_info, i))
|
|
continue;
|
|
this_leaf = CPUID4_INFO_IDX(i, index);
|
|
for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
|
|
if (!cpu_online(sibling))
|
|
continue;
|
|
set_bit(sibling, this_leaf->shared_cpu_map);
|
|
}
|
|
}
|
|
} else
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void cache_shared_cpu_map_setup(unsigned int cpu, int index)
|
|
{
|
|
struct _cpuid4_info *this_leaf, *sibling_leaf;
|
|
unsigned long num_threads_sharing;
|
|
int index_msb, i;
|
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
|
|
|
if (c->x86_vendor == X86_VENDOR_AMD) {
|
|
if (cache_shared_amd_cpu_map_setup(cpu, index))
|
|
return;
|
|
}
|
|
|
|
this_leaf = CPUID4_INFO_IDX(cpu, index);
|
|
num_threads_sharing = 1 + this_leaf->base.eax.split.num_threads_sharing;
|
|
|
|
if (num_threads_sharing == 1)
|
|
cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
|
|
else {
|
|
index_msb = get_count_order(num_threads_sharing);
|
|
|
|
for_each_online_cpu(i) {
|
|
if (cpu_data(i).apicid >> index_msb ==
|
|
c->apicid >> index_msb) {
|
|
cpumask_set_cpu(i,
|
|
to_cpumask(this_leaf->shared_cpu_map));
|
|
if (i != cpu && per_cpu(ici_cpuid4_info, i)) {
|
|
sibling_leaf =
|
|
CPUID4_INFO_IDX(i, index);
|
|
cpumask_set_cpu(cpu, to_cpumask(
|
|
sibling_leaf->shared_cpu_map));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
static void cache_remove_shared_cpu_map(unsigned int cpu, int index)
|
|
{
|
|
struct _cpuid4_info *this_leaf, *sibling_leaf;
|
|
int sibling;
|
|
|
|
this_leaf = CPUID4_INFO_IDX(cpu, index);
|
|
for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
|
|
sibling_leaf = CPUID4_INFO_IDX(sibling, index);
|
|
cpumask_clear_cpu(cpu,
|
|
to_cpumask(sibling_leaf->shared_cpu_map));
|
|
}
|
|
}
|
|
#else
|
|
static void cache_shared_cpu_map_setup(unsigned int cpu, int index)
|
|
{
|
|
}
|
|
|
|
static void cache_remove_shared_cpu_map(unsigned int cpu, int index)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
static void free_cache_attributes(unsigned int cpu)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < num_cache_leaves; i++)
|
|
cache_remove_shared_cpu_map(cpu, i);
|
|
|
|
kfree(per_cpu(ici_cpuid4_info, cpu));
|
|
per_cpu(ici_cpuid4_info, cpu) = NULL;
|
|
}
|
|
|
|
static void get_cpu_leaves(void *_retval)
|
|
{
|
|
int j, *retval = _retval, cpu = smp_processor_id();
|
|
|
|
/* Do cpuid and store the results */
|
|
for (j = 0; j < num_cache_leaves; j++) {
|
|
struct _cpuid4_info *this_leaf = CPUID4_INFO_IDX(cpu, j);
|
|
|
|
*retval = cpuid4_cache_lookup_regs(j, &this_leaf->base);
|
|
if (unlikely(*retval < 0)) {
|
|
int i;
|
|
|
|
for (i = 0; i < j; i++)
|
|
cache_remove_shared_cpu_map(cpu, i);
|
|
break;
|
|
}
|
|
cache_shared_cpu_map_setup(cpu, j);
|
|
}
|
|
}
|
|
|
|
static int detect_cache_attributes(unsigned int cpu)
|
|
{
|
|
int retval;
|
|
|
|
if (num_cache_leaves == 0)
|
|
return -ENOENT;
|
|
|
|
per_cpu(ici_cpuid4_info, cpu) = kzalloc(
|
|
sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
|
|
if (per_cpu(ici_cpuid4_info, cpu) == NULL)
|
|
return -ENOMEM;
|
|
|
|
smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
|
|
if (retval) {
|
|
kfree(per_cpu(ici_cpuid4_info, cpu));
|
|
per_cpu(ici_cpuid4_info, cpu) = NULL;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
#include <linux/kobject.h>
|
|
#include <linux/sysfs.h>
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#include <linux/cpu.h>
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/* pointer to kobject for cpuX/cache */
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static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
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struct _index_kobject {
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struct kobject kobj;
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unsigned int cpu;
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unsigned short index;
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};
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/* pointer to array of kobjects for cpuX/cache/indexY */
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static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
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#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y]))
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#define show_one_plus(file_name, object, val) \
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static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \
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unsigned int cpu) \
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{ \
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return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
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}
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show_one_plus(level, base.eax.split.level, 0);
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show_one_plus(coherency_line_size, base.ebx.split.coherency_line_size, 1);
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show_one_plus(physical_line_partition, base.ebx.split.physical_line_partition, 1);
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show_one_plus(ways_of_associativity, base.ebx.split.ways_of_associativity, 1);
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show_one_plus(number_of_sets, base.ecx.split.number_of_sets, 1);
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static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int cpu)
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{
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return sprintf(buf, "%luK\n", this_leaf->base.size / 1024);
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}
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static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
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int type, char *buf)
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{
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ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
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int n = 0;
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if (len > 1) {
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const struct cpumask *mask;
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mask = to_cpumask(this_leaf->shared_cpu_map);
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n = type ?
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cpulist_scnprintf(buf, len-2, mask) :
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cpumask_scnprintf(buf, len-2, mask);
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buf[n++] = '\n';
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buf[n] = '\0';
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}
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return n;
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}
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static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf,
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unsigned int cpu)
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{
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return show_shared_cpu_map_func(leaf, 0, buf);
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}
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static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf,
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unsigned int cpu)
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{
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return show_shared_cpu_map_func(leaf, 1, buf);
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}
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static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int cpu)
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{
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switch (this_leaf->base.eax.split.type) {
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case CACHE_TYPE_DATA:
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return sprintf(buf, "Data\n");
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case CACHE_TYPE_INST:
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return sprintf(buf, "Instruction\n");
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case CACHE_TYPE_UNIFIED:
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return sprintf(buf, "Unified\n");
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default:
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return sprintf(buf, "Unknown\n");
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}
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}
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#define to_object(k) container_of(k, struct _index_kobject, kobj)
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#define to_attr(a) container_of(a, struct _cache_attr, attr)
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#define define_one_ro(_name) \
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static struct _cache_attr _name = \
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__ATTR(_name, 0444, show_##_name, NULL)
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define_one_ro(level);
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define_one_ro(type);
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define_one_ro(coherency_line_size);
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define_one_ro(physical_line_partition);
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define_one_ro(ways_of_associativity);
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define_one_ro(number_of_sets);
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define_one_ro(size);
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define_one_ro(shared_cpu_map);
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define_one_ro(shared_cpu_list);
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static struct attribute *default_attrs[] = {
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&type.attr,
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&level.attr,
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&coherency_line_size.attr,
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&physical_line_partition.attr,
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&ways_of_associativity.attr,
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&number_of_sets.attr,
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&size.attr,
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&shared_cpu_map.attr,
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&shared_cpu_list.attr,
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NULL
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};
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#ifdef CONFIG_AMD_NB
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static struct attribute **amd_l3_attrs(void)
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{
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static struct attribute **attrs;
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int n;
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if (attrs)
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return attrs;
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n = ARRAY_SIZE(default_attrs);
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if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
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n += 2;
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if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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n += 1;
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attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL);
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if (attrs == NULL)
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return attrs = default_attrs;
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for (n = 0; default_attrs[n]; n++)
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attrs[n] = default_attrs[n];
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if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) {
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attrs[n++] = &cache_disable_0.attr;
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attrs[n++] = &cache_disable_1.attr;
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}
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if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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attrs[n++] = &subcaches.attr;
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return attrs;
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}
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#endif
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static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
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{
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struct _cache_attr *fattr = to_attr(attr);
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struct _index_kobject *this_leaf = to_object(kobj);
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ssize_t ret;
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ret = fattr->show ?
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fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
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buf, this_leaf->cpu) :
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0;
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return ret;
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}
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static ssize_t store(struct kobject *kobj, struct attribute *attr,
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const char *buf, size_t count)
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{
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struct _cache_attr *fattr = to_attr(attr);
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struct _index_kobject *this_leaf = to_object(kobj);
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ssize_t ret;
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ret = fattr->store ?
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fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
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buf, count, this_leaf->cpu) :
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0;
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return ret;
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}
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static const struct sysfs_ops sysfs_ops = {
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.show = show,
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.store = store,
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};
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static struct kobj_type ktype_cache = {
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.sysfs_ops = &sysfs_ops,
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.default_attrs = default_attrs,
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};
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static struct kobj_type ktype_percpu_entry = {
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.sysfs_ops = &sysfs_ops,
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};
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static void cpuid4_cache_sysfs_exit(unsigned int cpu)
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{
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kfree(per_cpu(ici_cache_kobject, cpu));
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kfree(per_cpu(ici_index_kobject, cpu));
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per_cpu(ici_cache_kobject, cpu) = NULL;
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per_cpu(ici_index_kobject, cpu) = NULL;
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free_cache_attributes(cpu);
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}
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static int cpuid4_cache_sysfs_init(unsigned int cpu)
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{
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int err;
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if (num_cache_leaves == 0)
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return -ENOENT;
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err = detect_cache_attributes(cpu);
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if (err)
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return err;
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/* Allocate all required memory */
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per_cpu(ici_cache_kobject, cpu) =
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kzalloc(sizeof(struct kobject), GFP_KERNEL);
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if (unlikely(per_cpu(ici_cache_kobject, cpu) == NULL))
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goto err_out;
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per_cpu(ici_index_kobject, cpu) = kzalloc(
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sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
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if (unlikely(per_cpu(ici_index_kobject, cpu) == NULL))
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goto err_out;
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return 0;
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err_out:
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cpuid4_cache_sysfs_exit(cpu);
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return -ENOMEM;
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}
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static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
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/* Add/Remove cache interface for CPU device */
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static int cache_add_dev(struct device *dev)
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{
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unsigned int cpu = dev->id;
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unsigned long i, j;
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struct _index_kobject *this_object;
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struct _cpuid4_info *this_leaf;
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int retval;
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retval = cpuid4_cache_sysfs_init(cpu);
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if (unlikely(retval < 0))
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return retval;
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retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu),
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&ktype_percpu_entry,
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&dev->kobj, "%s", "cache");
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if (retval < 0) {
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cpuid4_cache_sysfs_exit(cpu);
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return retval;
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}
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for (i = 0; i < num_cache_leaves; i++) {
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this_object = INDEX_KOBJECT_PTR(cpu, i);
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this_object->cpu = cpu;
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this_object->index = i;
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this_leaf = CPUID4_INFO_IDX(cpu, i);
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ktype_cache.default_attrs = default_attrs;
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#ifdef CONFIG_AMD_NB
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if (this_leaf->base.nb)
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ktype_cache.default_attrs = amd_l3_attrs();
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#endif
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retval = kobject_init_and_add(&(this_object->kobj),
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&ktype_cache,
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per_cpu(ici_cache_kobject, cpu),
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"index%1lu", i);
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if (unlikely(retval)) {
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for (j = 0; j < i; j++)
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kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
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kobject_put(per_cpu(ici_cache_kobject, cpu));
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cpuid4_cache_sysfs_exit(cpu);
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return retval;
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}
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kobject_uevent(&(this_object->kobj), KOBJ_ADD);
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}
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cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
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kobject_uevent(per_cpu(ici_cache_kobject, cpu), KOBJ_ADD);
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return 0;
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}
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static void cache_remove_dev(struct device *dev)
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{
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unsigned int cpu = dev->id;
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unsigned long i;
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if (per_cpu(ici_cpuid4_info, cpu) == NULL)
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return;
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if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
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return;
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cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
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for (i = 0; i < num_cache_leaves; i++)
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kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
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kobject_put(per_cpu(ici_cache_kobject, cpu));
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cpuid4_cache_sysfs_exit(cpu);
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}
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static int cacheinfo_cpu_callback(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned long)hcpu;
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struct device *dev;
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dev = get_cpu_device(cpu);
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switch (action) {
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case CPU_ONLINE:
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case CPU_ONLINE_FROZEN:
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cache_add_dev(dev);
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break;
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case CPU_DEAD:
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case CPU_DEAD_FROZEN:
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cache_remove_dev(dev);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block cacheinfo_cpu_notifier = {
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.notifier_call = cacheinfo_cpu_callback,
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};
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static int __init cache_sysfs_init(void)
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{
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int i;
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if (num_cache_leaves == 0)
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return 0;
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for_each_online_cpu(i) {
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int err;
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struct device *dev = get_cpu_device(i);
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err = cache_add_dev(dev);
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if (err)
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return err;
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}
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register_hotcpu_notifier(&cacheinfo_cpu_notifier);
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return 0;
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}
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device_initcall(cache_sysfs_init);
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#endif
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