55a68c23e0
It seems we made a mistake when creating dw_apb_timer_of.c:
picoxcell sched_clock had parts that were not related to
dw_apb_timer, yet we moved them to dw_apb_timer_of, and tried to
use them on socfpga.
This results in system where user/system time is not measured
properly, as demonstrated by
time dd if=/dev/urandom of=/dev/zero bs=100000 count=100
So this patch switches sched_clock to hardware that exists on both
platforms, and adds missing of_node_put() in dw_apb_timer_init().
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation
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* Copyright (c) 2011 Picochip Ltd., Jamie Iles
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*
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* Modified from mach-picoxcell/time.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/dw_apb_timer.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mach/time.h>
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#include <asm/sched_clock.h>
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static void timer_get_base_and_rate(struct device_node *np,
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void __iomem **base, u32 *rate)
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{
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*base = of_iomap(np, 0);
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if (!*base)
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panic("Unable to map regs for %s", np->name);
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if (of_property_read_u32(np, "clock-freq", rate) &&
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of_property_read_u32(np, "clock-frequency", rate))
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panic("No clock-frequency property for %s", np->name);
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}
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static void add_clockevent(struct device_node *event_timer)
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{
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void __iomem *iobase;
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struct dw_apb_clock_event_device *ced;
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u32 irq, rate;
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irq = irq_of_parse_and_map(event_timer, 0);
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if (irq == NO_IRQ)
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panic("No IRQ for clock event timer");
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timer_get_base_and_rate(event_timer, &iobase, &rate);
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ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
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rate);
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if (!ced)
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panic("Unable to initialise clockevent device");
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dw_apb_clockevent_register(ced);
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}
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static void __iomem *sched_io_base;
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/* This is actually same as __apbt_read_clocksource(), but with
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different interface */
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static u32 read_sched_clock_sptimer(void)
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{
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return ~__raw_readl(sched_io_base + APBTMR_N_CURRENT_VALUE);
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}
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static void add_clocksource(struct device_node *source_timer)
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{
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void __iomem *iobase;
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struct dw_apb_clocksource *cs;
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u32 rate;
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timer_get_base_and_rate(source_timer, &iobase, &rate);
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cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
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if (!cs)
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panic("Unable to initialise clocksource device");
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dw_apb_clocksource_start(cs);
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dw_apb_clocksource_register(cs);
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sched_io_base = iobase;
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setup_sched_clock(read_sched_clock_sptimer, 32, rate);
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}
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static const struct of_device_id osctimer_ids[] __initconst = {
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{ .compatible = "picochip,pc3x2-timer" },
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{ .compatible = "snps,dw-apb-timer-osc" },
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{ .compatible = "snps,dw-apb-timer-sp" },
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{ /* Sentinel */ },
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};
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/*
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You don't have to use dw_apb_timer for scheduler clock,
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this should also work fine on arm:
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twd_local_timer_of_register();
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arch_timer_of_register();
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arch_timer_sched_clock_init();
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*/
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void __init dw_apb_timer_init(void)
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{
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struct device_node *event_timer, *source_timer;
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event_timer = of_find_matching_node(NULL, osctimer_ids);
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if (!event_timer)
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panic("No timer for clockevent");
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add_clockevent(event_timer);
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source_timer = of_find_matching_node(event_timer, osctimer_ids);
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if (!source_timer)
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panic("No timer for clocksource");
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add_clocksource(source_timer);
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of_node_put(event_timer);
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of_node_put(source_timer);
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}
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