0a4081641d
All SOC device error interrupts are muxed and delivered to the core as a single MPIC error interrupt. Currently all the device drivers requiring access to device errors have to register for the MPIC error interrupt as a shared interrupt. With this patch we add interrupt demuxing capability in the mpic driver, allowing device drivers to register for their individual error interrupts. This is achieved by handling error interrupts in a cascaded fashion. MPIC error interrupt is handled by the "error_int_handler", which subsequently demuxes it using the EISR and delivers it to the respective drivers. The error interrupt capability is dependent on the MPIC EIMR register, which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error interrupt demuxing capability is dependent on the MPIC version and can be used for versions >= 4.1. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Varun Sethi <varun.sethi@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mpic.h>
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#include "mpic.h"
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#define MPIC_ERR_INT_BASE 0x3900
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#define MPIC_ERR_INT_EISR 0x0000
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#define MPIC_ERR_INT_EIMR 0x0010
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static inline u32 mpic_fsl_err_read(u32 __iomem *base, unsigned int err_reg)
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{
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return in_be32(base + (err_reg >> 2));
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}
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static inline void mpic_fsl_err_write(u32 __iomem *base, u32 value)
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{
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out_be32(base + (MPIC_ERR_INT_EIMR >> 2), value);
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}
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static void fsl_mpic_mask_err(struct irq_data *d)
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{
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u32 eimr;
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struct mpic *mpic = irq_data_get_irq_chip_data(d);
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unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
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eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
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eimr |= (1 << (31 - src));
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mpic_fsl_err_write(mpic->err_regs, eimr);
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}
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static void fsl_mpic_unmask_err(struct irq_data *d)
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{
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u32 eimr;
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struct mpic *mpic = irq_data_get_irq_chip_data(d);
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unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
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eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
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eimr &= ~(1 << (31 - src));
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mpic_fsl_err_write(mpic->err_regs, eimr);
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}
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static struct irq_chip fsl_mpic_err_chip = {
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.irq_disable = fsl_mpic_mask_err,
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.irq_mask = fsl_mpic_mask_err,
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.irq_unmask = fsl_mpic_unmask_err,
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};
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int mpic_setup_error_int(struct mpic *mpic, int intvec)
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{
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int i;
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mpic->err_regs = ioremap(mpic->paddr + MPIC_ERR_INT_BASE, 0x1000);
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if (!mpic->err_regs) {
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pr_err("could not map mpic error registers\n");
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return -ENOMEM;
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}
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mpic->hc_err = fsl_mpic_err_chip;
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mpic->hc_err.name = mpic->name;
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mpic->flags |= MPIC_FSL_HAS_EIMR;
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/* allocate interrupt vectors for error interrupts */
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for (i = MPIC_MAX_ERR - 1; i >= 0; i--)
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mpic->err_int_vecs[i] = --intvec;
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return 0;
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}
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int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
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{
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if ((mpic->flags & MPIC_FSL_HAS_EIMR) &&
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(hw >= mpic->err_int_vecs[0] &&
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hw <= mpic->err_int_vecs[MPIC_MAX_ERR - 1])) {
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WARN_ON(mpic->flags & MPIC_SECONDARY);
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pr_debug("mpic: mapping as Error Interrupt\n");
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irq_set_chip_data(virq, mpic);
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irq_set_chip_and_handler(virq, &mpic->hc_err,
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handle_level_irq);
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return 1;
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}
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return 0;
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}
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static irqreturn_t fsl_error_int_handler(int irq, void *data)
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{
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struct mpic *mpic = (struct mpic *) data;
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u32 eisr, eimr;
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int errint;
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unsigned int cascade_irq;
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eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
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eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
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if (!(eisr & ~eimr))
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return IRQ_NONE;
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while (eisr) {
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errint = __builtin_clz(eisr);
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cascade_irq = irq_linear_revmap(mpic->irqhost,
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mpic->err_int_vecs[errint]);
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WARN_ON(cascade_irq == NO_IRQ);
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if (cascade_irq != NO_IRQ) {
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generic_handle_irq(cascade_irq);
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} else {
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eimr |= 1 << (31 - errint);
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mpic_fsl_err_write(mpic->err_regs, eimr);
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}
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eisr &= ~(1 << (31 - errint));
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}
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return IRQ_HANDLED;
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}
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void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
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{
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unsigned int virq;
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int ret;
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virq = irq_create_mapping(mpic->irqhost, irqnum);
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if (virq == NO_IRQ) {
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pr_err("Error interrupt setup failed\n");
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return;
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}
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/* Mask all error interrupts */
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mpic_fsl_err_write(mpic->err_regs, ~0);
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ret = request_irq(virq, fsl_error_int_handler, IRQF_NO_THREAD,
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"mpic-error-int", mpic);
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if (ret)
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pr_err("Failed to register error interrupt handler\n");
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}
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