d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
181 lines
3.9 KiB
C
181 lines
3.9 KiB
C
/*
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* Interrupt controller support for IBM Spruce
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*
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* Authors: Mark Greer, Matt Porter, and Johnnie Peters
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* mgreer@mvista.com
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* mporter@mvista.com
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* jpeters@mvista.com
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*
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* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include "cpc700.h"
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static void
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cpc700_unmask_irq(unsigned int irq)
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{
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unsigned int tr_bits;
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/*
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* IRQ 31 is largest IRQ supported.
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* IRQs 17-19 are reserved.
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*/
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if ((irq <= 31) && ((irq < 17) || (irq > 19))) {
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tr_bits = CPC700_IN_32(CPC700_UIC_UICTR);
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if ((tr_bits & (1 << (31 - irq))) == 0) {
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/* level trigger interrupt, clear bit in status
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* register */
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CPC700_OUT_32(CPC700_UIC_UICSR, 1 << (31 - irq));
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}
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/* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
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ppc_cached_irq_mask[0] |= CPC700_UIC_IRQ_BIT(irq);
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CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
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}
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return;
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}
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static void
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cpc700_mask_irq(unsigned int irq)
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{
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/*
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* IRQ 31 is largest IRQ supported.
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* IRQs 17-19 are reserved.
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*/
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if ((irq <= 31) && ((irq < 17) || (irq > 19))) {
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/* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
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ppc_cached_irq_mask[0] &=
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~CPC700_UIC_IRQ_BIT(irq);
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CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
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}
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return;
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}
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static void
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cpc700_mask_and_ack_irq(unsigned int irq)
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{
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u_int bit;
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/*
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* IRQ 31 is largest IRQ supported.
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* IRQs 17-19 are reserved.
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*/
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if ((irq <= 31) && ((irq < 17) || (irq > 19))) {
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/* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
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bit = CPC700_UIC_IRQ_BIT(irq);
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ppc_cached_irq_mask[0] &= ~bit;
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CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
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CPC700_OUT_32(CPC700_UIC_UICSR, bit); /* Write 1 clears IRQ */
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}
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return;
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}
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static struct hw_interrupt_type cpc700_pic = {
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.typename = "CPC700 PIC",
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.enable = cpc700_unmask_irq,
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.disable = cpc700_mask_irq,
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.ack = cpc700_mask_and_ack_irq,
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};
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__init static void
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cpc700_pic_init_irq(unsigned int irq)
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{
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unsigned int tmp;
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/* Set interrupt sense */
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tmp = CPC700_IN_32(CPC700_UIC_UICTR);
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if (cpc700_irq_assigns[irq][0] == 0) {
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tmp &= ~CPC700_UIC_IRQ_BIT(irq);
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} else {
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tmp |= CPC700_UIC_IRQ_BIT(irq);
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}
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CPC700_OUT_32(CPC700_UIC_UICTR, tmp);
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/* Set interrupt polarity */
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tmp = CPC700_IN_32(CPC700_UIC_UICPR);
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if (cpc700_irq_assigns[irq][1]) {
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tmp |= CPC700_UIC_IRQ_BIT(irq);
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} else {
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tmp &= ~CPC700_UIC_IRQ_BIT(irq);
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}
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CPC700_OUT_32(CPC700_UIC_UICPR, tmp);
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/* Set interrupt critical */
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tmp = CPC700_IN_32(CPC700_UIC_UICCR);
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tmp |= CPC700_UIC_IRQ_BIT(irq);
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CPC700_OUT_32(CPC700_UIC_UICCR, tmp);
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return;
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}
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__init void
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cpc700_init_IRQ(void)
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{
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int i;
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ppc_cached_irq_mask[0] = 0;
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CPC700_OUT_32(CPC700_UIC_UICER, 0x00000000); /* Disable all irq's */
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CPC700_OUT_32(CPC700_UIC_UICSR, 0xffffffff); /* Clear cur intrs */
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CPC700_OUT_32(CPC700_UIC_UICCR, 0xffffffff); /* Gen INT not MCP */
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CPC700_OUT_32(CPC700_UIC_UICPR, 0x00000000); /* Active low */
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CPC700_OUT_32(CPC700_UIC_UICTR, 0x00000000); /* Level Sensitive */
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CPC700_OUT_32(CPC700_UIC_UICVR, CPC700_UIC_UICVCR_0_HI);
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/* IRQ 0 is highest */
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for (i = 0; i < 17; i++) {
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irq_desc[i].chip = &cpc700_pic;
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cpc700_pic_init_irq(i);
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}
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for (i = 20; i < 32; i++) {
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irq_desc[i].chip = &cpc700_pic;
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cpc700_pic_init_irq(i);
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}
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return;
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}
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/*
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* Find the highest IRQ that generating an interrupt, if any.
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*/
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int
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cpc700_get_irq(struct pt_regs *regs)
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{
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int irq = 0;
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u_int irq_status, irq_test = 1;
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irq_status = CPC700_IN_32(CPC700_UIC_UICMSR);
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do
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{
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if (irq_status & irq_test)
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break;
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irq++;
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irq_test <<= 1;
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} while (irq < NR_IRQS);
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if (irq == NR_IRQS)
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irq = 33;
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return (31 - irq);
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}
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