540b573875
Currently, the documented kernel entry requirements are not explicit about whether the kernel should be entered in ARM or Thumb, leading to an ambiguitity about how to enter Thumb-2 kernels. As a result, the kernel is reliant on the zImage decompressor to enter the kernel proper in the correct instruction set state. This patch changes the boot entry protocol for head.S and Image to be the same as for zImage: in all cases, the kernel is now entered in ARM. Documentation/arm/Booting is updated to reflect this new policy. A different rule will be needed for Cortex-M class CPUs as and when support for those lands in mainline, since these CPUs don't support the ARM instruction set at all: a note is added to the effect that the kernel must be entered in Thumb on such systems. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
600 lines
15 KiB
ArmAsm
600 lines
15 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Kernel startup code for all 32-bit CPUs
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/domain.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/system.h>
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#ifdef CONFIG_DEBUG_LL
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#include <mach/debug-macro.S>
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#endif
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/*
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* swapper_pg_dir is the virtual address of the initial page table.
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* We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
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* make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
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* the least significant 16 bits to be 0x8000, but we could probably
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* relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
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*/
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
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#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
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#error KERNEL_RAM_VADDR must start at 0xXXXX8000
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
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.macro pgtbl, rd, phys
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add \rd, \phys, #TEXT_OFFSET - 0x4000
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.endm
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#ifdef CONFIG_XIP_KERNEL
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#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
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#define KERNEL_END _edata_loc
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#else
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#define KERNEL_START KERNEL_RAM_VADDR
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#define KERNEL_END _end
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr, r2 = atags or dtb pointer.
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*
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* This code is mostly position independent, so if you link the kernel at
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* 0xc0008000, you call this at __pa(0xc0008000).
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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* We're trying to keep crap to a minimum; DO NOT add any machine specific
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* crap here - that's what the boot loader (or in extreme, well justified
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* circumstances, zImage) is for.
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*/
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.arm
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__HEAD
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ENTRY(stext)
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THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(1: )
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
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@ and irqs disabled
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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THUMB( it eq ) @ force fixup-able long branch encoding
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beq __error_p @ yes, error 'p'
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#ifndef CONFIG_XIP_KERNEL
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adr r3, 2f
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ldmia r3, {r4, r8}
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sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
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add r8, r8, r4 @ PHYS_OFFSET
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#else
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ldr r8, =PLAT_PHYS_OFFSET
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#endif
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/*
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* r1 = machine no, r2 = atags or dtb,
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* r8 = phys_offset, r9 = cpuid, r10 = procinfo
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*/
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bl __vet_atags
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#ifdef CONFIG_SMP_ON_UP
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bl __fixup_smp
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#endif
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
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bl __fixup_pv_table
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#endif
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bl __create_page_tables
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
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* xxx_proc_info structure selected by __lookup_processor_type
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* above. On return, the CPU will be ready for the MMU to be
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* turned on, and r0 will hold the CPU control register value.
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*/
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ldr r13, =__mmap_switched @ address to jump to after
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@ mmu has been enabled
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adr lr, BSYM(1f) @ return (PIC) address
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mov r8, r4 @ set TTBR1 to swapper_pg_dir
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ARM( add pc, r10, #PROCINFO_INITFUNC )
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THUMB( add r12, r10, #PROCINFO_INITFUNC )
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THUMB( mov pc, r12 )
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1: b __enable_mmu
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ENDPROC(stext)
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.ltorg
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#ifndef CONFIG_XIP_KERNEL
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2: .long .
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.long PAGE_OFFSET
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#endif
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/*
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* Setup the initial page tables. We only setup the barest
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* amount which are required to get the kernel running, which
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* generally means mapping in the kernel code.
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*
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* r8 = phys_offset, r9 = cpuid, r10 = procinfo
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*
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* Returns:
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* r0, r3, r5-r7 corrupted
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* r4 = physical page table address
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*/
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__create_page_tables:
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pgtbl r4, r8 @ page table address
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/*
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* Clear the 16K level 1 swapper page table
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*/
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mov r0, r4
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mov r3, #0
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add r6, r0, #0x4000
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1: str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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teq r0, r6
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bne 1b
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ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
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/*
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* Create identity mapping to cater for __enable_mmu.
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* This identity mapping will be removed by paging_init().
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*/
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adr r0, __enable_mmu_loc
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ldmia r0, {r3, r5, r6}
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sub r0, r0, r3 @ virt->phys offset
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add r5, r5, r0 @ phys __enable_mmu
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add r6, r6, r0 @ phys __enable_mmu_end
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mov r5, r5, lsr #20
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mov r6, r6, lsr #20
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1: orr r3, r7, r5, lsl #20 @ flags + kernel base
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str r3, [r4, r5, lsl #2] @ identity mapping
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teq r5, r6
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addne r5, r5, #1 @ next section
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bne 1b
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/*
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* Now setup the pagetables for our kernel direct
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* mapped region.
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*/
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mov r3, pc
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mov r3, r3, lsr #20
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orr r3, r7, r3, lsl #20
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add r0, r4, #(KERNEL_START & 0xff000000) >> 18
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str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
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ldr r6, =(KERNEL_END - 1)
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add r0, r0, #4
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add r6, r4, r6, lsr #18
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1: cmp r0, r6
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add r3, r3, #1 << 20
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strls r3, [r0], #4
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bls 1b
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#ifdef CONFIG_XIP_KERNEL
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/*
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* Map some ram to cover our .data and .bss areas.
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*/
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add r3, r8, #TEXT_OFFSET
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orr r3, r3, r7
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add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
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str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
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ldr r6, =(_end - 1)
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add r0, r0, #4
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add r6, r4, r6, lsr #18
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1: cmp r0, r6
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add r3, r3, #1 << 20
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strls r3, [r0], #4
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bls 1b
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#endif
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/*
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* Then map boot params address in r2 or
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* the first 1MB of ram if boot params address is not specified.
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*/
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mov r0, r2, lsr #20
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movs r0, r0, lsl #20
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moveq r0, r8
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sub r3, r0, r8
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add r3, r3, #PAGE_OFFSET
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add r3, r4, r3, lsr #18
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orr r6, r7, r0
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str r6, [r3]
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#ifdef CONFIG_DEBUG_LL
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#ifndef CONFIG_DEBUG_ICEDCC
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/*
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* Map in IO space for serial debugging.
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* This allows debug messages to be output
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* via a serial console before paging_init.
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*/
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addruart r7, r3
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mov r3, r3, lsr #20
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mov r3, r3, lsl #2
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add r0, r4, r3
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rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
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cmp r3, #0x0800 @ limit to 512MB
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movhi r3, #0x0800
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add r6, r0, r3
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mov r3, r7, lsr #20
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ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
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orr r3, r7, r3, lsl #20
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1: str r3, [r0], #4
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add r3, r3, #1 << 20
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teq r0, r6
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bne 1b
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#else /* CONFIG_DEBUG_ICEDCC */
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/* we don't need any serial debugging mappings for ICEDCC */
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ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
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#endif /* !CONFIG_DEBUG_ICEDCC */
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#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
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/*
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* If we're using the NetWinder or CATS, we also need to map
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* in the 16550-type serial port for the debug messages
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*/
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add r0, r4, #0xff000000 >> 18
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orr r3, r7, #0x7c000000
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str r3, [r0]
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#endif
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#ifdef CONFIG_ARCH_RPC
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/*
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* Map in screen at 0x02000000 & SCREEN2_BASE
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* Similar reasons here - for debug. This is
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* only for Acorn RiscPC architectures.
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*/
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add r0, r4, #0x02000000 >> 18
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orr r3, r7, #0x02000000
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str r3, [r0]
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add r0, r4, #0xd8000000 >> 18
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str r3, [r0]
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#endif
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#endif
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mov pc, lr
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ENDPROC(__create_page_tables)
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.ltorg
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.align
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__enable_mmu_loc:
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.long .
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.long __enable_mmu
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.long __enable_mmu_end
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#if defined(CONFIG_SMP)
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__CPUINIT
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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THUMB( it eq ) @ force fixup-able long branch encoding
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beq __error_p
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/*
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* Use the page tables supplied from __cpu_up.
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*/
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adr r4, __secondary_data
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ldmia r4, {r5, r7, r12} @ address to jump to after
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sub lr, r4, r5 @ mmu has been enabled
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ldr r4, [r7, lr] @ get secondary_data.pgdir
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add r7, r7, #4
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ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
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adr lr, BSYM(__enable_mmu) @ return address
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mov r13, r12 @ __secondary_switched address
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ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
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@ (return control reg)
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THUMB( add r12, r10, #PROCINFO_INITFUNC )
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THUMB( mov pc, r12 )
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ENDPROC(secondary_startup)
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/*
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* r6 = &secondary_data
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*/
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ENTRY(__secondary_switched)
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ldr sp, [r7, #4] @ get secondary_data.stack
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mov fp, #0
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b secondary_start_kernel
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ENDPROC(__secondary_switched)
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.align
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.type __secondary_data, %object
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__secondary_data:
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.long .
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.long secondary_data
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.long __secondary_switched
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#endif /* defined(CONFIG_SMP) */
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/*
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* Setup common bits before finally enabling the MMU. Essentially
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* this is just loading the page table pointer and domain access
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* registers.
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*
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* r0 = cp#15 control register
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* r1 = machine ID
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* r2 = atags or dtb pointer
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* r4 = page table pointer
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* r9 = processor ID
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* r13 = *virtual* address to jump to upon completion
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*/
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__enable_mmu:
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#ifdef CONFIG_ALIGNMENT_TRAP
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orr r0, r0, #CR_A
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#else
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bic r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CR_C
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #CR_Z
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT))
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mcr p15, 0, r5, c3, c0, 0 @ load domain access register
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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b __turn_mmu_on
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ENDPROC(__enable_mmu)
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/*
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* Enable the MMU. This completely changes the structure of the visible
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* memory space. You will not be able to trace execution through this.
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* If you have an enquiry about this, *please* check the linux-arm-kernel
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* mailing list archives BEFORE sending another post to the list.
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*
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* r0 = cp#15 control register
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* r1 = machine ID
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* r2 = atags or dtb pointer
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* r9 = processor ID
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* r13 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
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*/
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.align 5
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__turn_mmu_on:
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mrc p15, 0, r3, c0, c0, 0 @ read id reg
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mov r3, r3
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mov r3, r13
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mov pc, r3
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__enable_mmu_end:
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ENDPROC(__turn_mmu_on)
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#ifdef CONFIG_SMP_ON_UP
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__INIT
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__fixup_smp:
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and r3, r9, #0x000f0000 @ architecture version
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teq r3, #0x000f0000 @ CPU ID supported?
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bne __fixup_smp_on_up @ no, assume UP
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bic r3, r9, #0x00ff0000
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bic r3, r3, #0x0000000f @ mask 0xff00fff0
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mov r4, #0x41000000
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orr r4, r4, #0x0000b000
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orr r4, r4, #0x00000020 @ val 0x4100b020
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teq r3, r4 @ ARM 11MPCore?
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moveq pc, lr @ yes, assume SMP
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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and r0, r0, #0xc0000000 @ multiprocessing extensions and
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teq r0, #0x80000000 @ not part of a uniprocessor system?
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moveq pc, lr @ yes, assume SMP
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__fixup_smp_on_up:
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adr r0, 1f
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ldmia r0, {r3 - r5}
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sub r3, r0, r3
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add r4, r4, r3
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add r5, r5, r3
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b __do_fixup_smp_on_up
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ENDPROC(__fixup_smp)
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.align
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1: .word .
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.word __smpalt_begin
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.word __smpalt_end
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.pushsection .data
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.globl smp_on_up
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smp_on_up:
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ALT_SMP(.long 1)
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ALT_UP(.long 0)
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.popsection
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#endif
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.text
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__do_fixup_smp_on_up:
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cmp r4, r5
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movhs pc, lr
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ldmia r4!, {r0, r6}
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ARM( str r6, [r0, r3] )
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THUMB( add r0, r0, r3 )
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#ifdef __ARMEB__
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THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
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#endif
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THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
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THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
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THUMB( strh r6, [r0] )
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b __do_fixup_smp_on_up
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ENDPROC(__do_fixup_smp_on_up)
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ENTRY(fixup_smp)
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stmfd sp!, {r4 - r6, lr}
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mov r4, r0
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add r5, r0, r1
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mov r3, #0
|
|
bl __do_fixup_smp_on_up
|
|
ldmfd sp!, {r4 - r6, pc}
|
|
ENDPROC(fixup_smp)
|
|
|
|
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
|
|
|
|
/* __fixup_pv_table - patch the stub instructions with the delta between
|
|
* PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
|
|
* can be expressed by an immediate shifter operand. The stub instruction
|
|
* has a form of '(add|sub) rd, rn, #imm'.
|
|
*/
|
|
__HEAD
|
|
__fixup_pv_table:
|
|
adr r0, 1f
|
|
ldmia r0, {r3-r5, r7}
|
|
sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
|
|
add r4, r4, r3 @ adjust table start address
|
|
add r5, r5, r3 @ adjust table end address
|
|
add r7, r7, r3 @ adjust __pv_phys_offset address
|
|
str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
|
|
#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
|
|
mov r6, r3, lsr #24 @ constant for add/sub instructions
|
|
teq r3, r6, lsl #24 @ must be 16MiB aligned
|
|
#else
|
|
mov r6, r3, lsr #16 @ constant for add/sub instructions
|
|
teq r3, r6, lsl #16 @ must be 64kiB aligned
|
|
#endif
|
|
THUMB( it ne @ cross section branch )
|
|
bne __error
|
|
str r6, [r7, #4] @ save to __pv_offset
|
|
b __fixup_a_pv_table
|
|
ENDPROC(__fixup_pv_table)
|
|
|
|
.align
|
|
1: .long .
|
|
.long __pv_table_begin
|
|
.long __pv_table_end
|
|
2: .long __pv_phys_offset
|
|
|
|
.text
|
|
__fixup_a_pv_table:
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
|
|
lsls r0, r6, #24
|
|
lsr r6, #8
|
|
beq 1f
|
|
clz r7, r0
|
|
lsr r0, #24
|
|
lsl r0, r7
|
|
bic r0, 0x0080
|
|
lsrs r7, #1
|
|
orrcs r0, #0x0080
|
|
orr r0, r0, r7, lsl #12
|
|
#endif
|
|
1: lsls r6, #24
|
|
beq 4f
|
|
clz r7, r6
|
|
lsr r6, #24
|
|
lsl r6, r7
|
|
bic r6, #0x0080
|
|
lsrs r7, #1
|
|
orrcs r6, #0x0080
|
|
orr r6, r6, r7, lsl #12
|
|
orr r6, #0x4000
|
|
b 4f
|
|
2: @ at this point the C flag is always clear
|
|
add r7, r3
|
|
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
|
|
ldrh ip, [r7]
|
|
tst ip, 0x0400 @ the i bit tells us LS or MS byte
|
|
beq 3f
|
|
cmp r0, #0 @ set C flag, and ...
|
|
biceq ip, 0x0400 @ immediate zero value has a special encoding
|
|
streqh ip, [r7] @ that requires the i bit cleared
|
|
#endif
|
|
3: ldrh ip, [r7, #2]
|
|
and ip, 0x8f00
|
|
orrcc ip, r6 @ mask in offset bits 31-24
|
|
orrcs ip, r0 @ mask in offset bits 23-16
|
|
strh ip, [r7, #2]
|
|
4: cmp r4, r5
|
|
ldrcc r7, [r4], #4 @ use branch for delay slot
|
|
bcc 2b
|
|
bx lr
|
|
#else
|
|
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
|
|
and r0, r6, #255 @ offset bits 23-16
|
|
mov r6, r6, lsr #8 @ offset bits 31-24
|
|
#else
|
|
mov r0, #0 @ just in case...
|
|
#endif
|
|
b 3f
|
|
2: ldr ip, [r7, r3]
|
|
bic ip, ip, #0x000000ff
|
|
tst ip, #0x400 @ rotate shift tells us LS or MS byte
|
|
orrne ip, ip, r6 @ mask in offset bits 31-24
|
|
orreq ip, ip, r0 @ mask in offset bits 23-16
|
|
str ip, [r7, r3]
|
|
3: cmp r4, r5
|
|
ldrcc r7, [r4], #4 @ use branch for delay slot
|
|
bcc 2b
|
|
mov pc, lr
|
|
#endif
|
|
ENDPROC(__fixup_a_pv_table)
|
|
|
|
ENTRY(fixup_pv_table)
|
|
stmfd sp!, {r4 - r7, lr}
|
|
ldr r2, 2f @ get address of __pv_phys_offset
|
|
mov r3, #0 @ no offset
|
|
mov r4, r0 @ r0 = table start
|
|
add r5, r0, r1 @ r1 = table size
|
|
ldr r6, [r2, #4] @ get __pv_offset
|
|
bl __fixup_a_pv_table
|
|
ldmfd sp!, {r4 - r7, pc}
|
|
ENDPROC(fixup_pv_table)
|
|
|
|
.align
|
|
2: .long __pv_phys_offset
|
|
|
|
.data
|
|
.globl __pv_phys_offset
|
|
.type __pv_phys_offset, %object
|
|
__pv_phys_offset:
|
|
.long 0
|
|
.size __pv_phys_offset, . - __pv_phys_offset
|
|
__pv_offset:
|
|
.long 0
|
|
#endif
|
|
|
|
#include "head-common.S"
|