89a82ef87e
This patchs allows to combine the AES and SHA hardware accelerators on some Atmel SoCs. Doing so, AES blocks are only written to/read from the AES hardware. Those blocks are also transferred from the AES to the SHA accelerator internally, without additionnal accesses to the system busses. Hence, the AES and SHA accelerators work in parallel to process all the data blocks, instead of serializing the process by (de)crypting those blocks first then authenticating them after like the generic crypto/authenc.c driver does. Of course, both the AES and SHA hardware accelerators need to be available before we can start to process the data blocks. Hence we use their crypto request queue to synchronize both drivers. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
92 lines
3 KiB
C
92 lines
3 KiB
C
#ifndef __ATMEL_AES_REGS_H__
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#define __ATMEL_AES_REGS_H__
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#define AES_CR 0x00
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#define AES_CR_START (1 << 0)
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#define AES_CR_SWRST (1 << 8)
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#define AES_CR_LOADSEED (1 << 16)
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#define AES_MR 0x04
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#define AES_MR_CYPHER_DEC (0 << 0)
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#define AES_MR_CYPHER_ENC (1 << 0)
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#define AES_MR_GTAGEN (1 << 1)
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#define AES_MR_DUALBUFF (1 << 3)
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#define AES_MR_PROCDLY_MASK (0xF << 4)
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#define AES_MR_PROCDLY_OFFSET 4
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#define AES_MR_SMOD_MASK (0x3 << 8)
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#define AES_MR_SMOD_MANUAL (0x0 << 8)
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#define AES_MR_SMOD_AUTO (0x1 << 8)
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#define AES_MR_SMOD_IDATAR0 (0x2 << 8)
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#define AES_MR_KEYSIZE_MASK (0x3 << 10)
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#define AES_MR_KEYSIZE_128 (0x0 << 10)
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#define AES_MR_KEYSIZE_192 (0x1 << 10)
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#define AES_MR_KEYSIZE_256 (0x2 << 10)
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#define AES_MR_OPMOD_MASK (0x7 << 12)
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#define AES_MR_OPMOD_ECB (0x0 << 12)
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#define AES_MR_OPMOD_CBC (0x1 << 12)
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#define AES_MR_OPMOD_OFB (0x2 << 12)
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#define AES_MR_OPMOD_CFB (0x3 << 12)
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#define AES_MR_OPMOD_CTR (0x4 << 12)
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#define AES_MR_OPMOD_GCM (0x5 << 12)
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#define AES_MR_OPMOD_XTS (0x6 << 12)
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#define AES_MR_LOD (0x1 << 15)
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#define AES_MR_CFBS_MASK (0x7 << 16)
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#define AES_MR_CFBS_128b (0x0 << 16)
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#define AES_MR_CFBS_64b (0x1 << 16)
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#define AES_MR_CFBS_32b (0x2 << 16)
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#define AES_MR_CFBS_16b (0x3 << 16)
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#define AES_MR_CFBS_8b (0x4 << 16)
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#define AES_MR_CKEY_MASK (0xF << 20)
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#define AES_MR_CKEY_OFFSET 20
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#define AES_MR_CMTYP_MASK (0x1F << 24)
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#define AES_MR_CMTYP_OFFSET 24
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#define AES_IER 0x10
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#define AES_IDR 0x14
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#define AES_IMR 0x18
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#define AES_ISR 0x1C
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#define AES_INT_DATARDY (1 << 0)
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#define AES_INT_URAD (1 << 8)
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#define AES_INT_TAGRDY (1 << 16)
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#define AES_ISR_URAT_MASK (0xF << 12)
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#define AES_ISR_URAT_IDR_WR_PROC (0x0 << 12)
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#define AES_ISR_URAT_ODR_RD_PROC (0x1 << 12)
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#define AES_ISR_URAT_MR_WR_PROC (0x2 << 12)
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#define AES_ISR_URAT_ODR_RD_SUBK (0x3 << 12)
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#define AES_ISR_URAT_MR_WR_SUBK (0x4 << 12)
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#define AES_ISR_URAT_WOR_RD (0x5 << 12)
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#define AES_KEYWR(x) (0x20 + ((x) * 0x04))
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#define AES_IDATAR(x) (0x40 + ((x) * 0x04))
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#define AES_ODATAR(x) (0x50 + ((x) * 0x04))
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#define AES_IVR(x) (0x60 + ((x) * 0x04))
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#define AES_AADLENR 0x70
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#define AES_CLENR 0x74
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#define AES_GHASHR(x) (0x78 + ((x) * 0x04))
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#define AES_TAGR(x) (0x88 + ((x) * 0x04))
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#define AES_CTRR 0x98
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#define AES_GCMHR(x) (0x9c + ((x) * 0x04))
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#define AES_EMR 0xb0
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#define AES_EMR_APEN BIT(0) /* Auto Padding Enable */
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#define AES_EMR_APM BIT(1) /* Auto Padding Mode */
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#define AES_EMR_APM_IPSEC 0x0
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#define AES_EMR_APM_SSL BIT(1)
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#define AES_EMR_PLIPEN BIT(4) /* PLIP Enable */
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#define AES_EMR_PLIPD BIT(5) /* PLIP Decipher */
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#define AES_EMR_PADLEN_MASK (0xFu << 8)
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#define AES_EMR_PADLEN_OFFSET 8
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#define AES_EMR_PADLEN(padlen) (((padlen) << AES_EMR_PADLEN_OFFSET) &\
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AES_EMR_PADLEN_MASK)
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#define AES_EMR_NHEAD_MASK (0xFu << 16)
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#define AES_EMR_NHEAD_OFFSET 16
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#define AES_EMR_NHEAD(nhead) (((nhead) << AES_EMR_NHEAD_OFFSET) &\
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AES_EMR_NHEAD_MASK)
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#define AES_TWR(x) (0xc0 + ((x) * 0x04))
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#define AES_ALPHAR(x) (0xd0 + ((x) * 0x04))
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#define AES_HW_VERSION 0xFC
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#endif /* __ATMEL_AES_REGS_H__ */
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