ec80fb2d89
This patch simply adds sdhci node to the device tree. We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
475 lines
10 KiB
Text
475 lines
10 KiB
Text
/*
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* MPC8536 DS Device Tree Source
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*
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,mpc8536ds";
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compatible = "fsl,mpc8536ds";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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pci3 = &pci3;
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};
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8536@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0 0 0>; // Filled by U-Boot
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};
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soc@fffe00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8536-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8536-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 0x2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8536-l2-cache-controller";
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reg = <0x20000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <16 0x2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0 0x1>;
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interrupt-parent = <&mpic>;
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};
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
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reg = <0x21300 4>;
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ranges = <0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8536-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8536-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8536-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8536-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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usb@22000 {
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compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
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reg = <0x22000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <28 0x2>;
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phy_type = "ulpi";
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};
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usb@23000 {
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compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <46 0x2>;
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phy_type = "ulpi";
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <10 0x1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <10 0x1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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ranges = <0x0 0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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usb@2b000 {
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compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
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reg = <0x2b000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <60 0x2>;
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dr_mode = "peripheral";
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phy_type = "ulpi";
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};
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sdhci@2e000 {
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compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <72 0x2>;
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interrupt-parent = <&mpic>;
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clock-frequency = <250000000>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 0x2>;
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interrupt-parent = <&mpic>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2 58 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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sata@18000 {
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compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
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reg = <0x18000 0x1000>;
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cell-index = <1>;
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interrupts = <74 0x2>;
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interrupt-parent = <&mpic>;
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};
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sata@19000 {
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compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
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reg = <0x19000 0x1000>;
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cell-index = <2>;
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interrupts = <41 0x2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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msi@41600 {
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compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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};
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pci0: pci@fffe08000 {
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 J17 Slot 1 */
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0x8800 0 0 1 &mpic 1 1
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0x8800 0 0 2 &mpic 2 1
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0x8800 0 0 3 &mpic 3 1
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0x8800 0 0 4 &mpic 4 1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 0x2>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
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0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xffe08000 0 0x1000>;
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};
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pci1: pcie@fffe09000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xffe09000 0 0x1000>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
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0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <25 0x2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 4 1
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0000 0 0 2 &mpic 5 1
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0000 0 0 3 &mpic 6 1
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0000 0 0 4 &mpic 7 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xf8000000
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0x02000000 0 0xf8000000
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0 0x08000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci2: pcie@fffe0a000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xffe0a000 0 0x1000>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
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0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 0x2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xf8000000
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0x02000000 0 0xf8000000
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0 0x08000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci3: pcie@fffe0b000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf 0xffe0b000 0 0x1000>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
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0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <27 0x2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 8 1
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0000 0 0 2 &mpic 9 1
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0000 0 0 3 &mpic 10 1
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0000 0 0 4 &mpic 11 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00100000>;
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};
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};
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};
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