Jayachandran C 51d1eac0cd MIPS: Netlogic: SMP wakeup code update ... Update for core intialization code. Initialize status register after receiving NMI for CPU wakeup. Add the low level L1D flush code before enabling threads in core. Also convert the ehb to _ehb so that it works under more GCC versions. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3755/ Patchwork: https://patchwork.linux-mips.org/patch/4095/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2012-07-24 17:28:47 +02:00
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common	MIPS: Netlogic: SMP wakeup code update	2012-07-24 17:28:47 +02:00
xlp	MIPS: Netlogic: Fix TLB size of boot CPU.	2012-07-03 19:04:02 +02:00
xlr	MIPS: Netlogic: Merge some of XLR/XLP wakup code	2011-12-07 22:04:56 +00:00
Kconfig	MIPS: Netlogic: Use CPU_XLR instead of NLM_XLR	2011-12-07 22:04:55 +00:00
Makefile	MIPS: Netlogic: Add XLP makefiles and config	2011-12-07 22:04:56 +00:00
Platform	MIPS: Netlogic: Add XLP makefiles and config	2011-12-07 22:04:56 +00:00