a0fba3eb05
The sparc64 spinlock_64.h contains a number of operations defined first as static inline functions, and then as macros with the same names and parameters as the functions. Maybe this was needed at some point in the past, but now nothing seems to depend on these macros (checked with a recursive grep looking for ifdefs on these names). Other archs don't define these identity-macros. So this patch deletes these unnecessary macros. Compile-tested with sparc64_defconfig. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: David S. Miller <davem@davemloft.net>
225 lines
4.4 KiB
C
225 lines
4.4 KiB
C
/* spinlock.h: 64-bit Sparc spinlock support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __SPARC64_SPINLOCK_H
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#define __SPARC64_SPINLOCK_H
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#ifndef __ASSEMBLY__
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/* To get debugging spinlocks which detect and catch
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* deadlock situations, set CONFIG_DEBUG_SPINLOCK
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* and rebuild your kernel.
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*/
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/* Because we play games to save cycles in the non-contention case, we
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* need to be extra careful about branch targets into the "spinning"
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* code. They live in their own section, but the newer V9 branches
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* have a shorter range than the traditional 32-bit sparc branch
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* variants. The rule is that the branches that go into and out of
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* the spinner sections must be pre-V9 branches.
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*/
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#define arch_spin_is_locked(lp) ((lp)->lock != 0)
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#define arch_spin_unlock_wait(lp) \
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do { rmb(); \
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} while((lp)->lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldstub [%1], %0\n"
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" brnz,pn %0, 2f\n"
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" nop\n"
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" .subsection 2\n"
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"2: ldub [%1], %0\n"
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" brnz,pt %0, 2b\n"
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" nop\n"
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" ba,a,pt %%xcc, 1b\n"
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" .previous"
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: "=&r" (tmp)
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: "r" (lock)
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: "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned long result;
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__asm__ __volatile__(
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" ldstub [%1], %0\n"
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: "=r" (result)
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: "r" (lock)
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: "memory");
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return (result == 0UL);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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__asm__ __volatile__(
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" stb %%g0, [%0]"
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: /* No outputs */
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: "r" (lock)
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: "memory");
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}
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static inline void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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"1: ldstub [%2], %0\n"
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" brnz,pn %0, 2f\n"
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" nop\n"
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" .subsection 2\n"
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"2: rdpr %%pil, %1\n"
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" wrpr %3, %%pil\n"
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"3: ldub [%2], %0\n"
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" brnz,pt %0, 3b\n"
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" nop\n"
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" ba,pt %%xcc, 1b\n"
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" wrpr %1, %%pil\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r"(lock), "r"(flags)
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: "memory");
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}
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/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
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static void inline arch_read_lock(arch_rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__ (
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"1: ldsw [%2], %0\n"
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" brlz,pn %0, 2f\n"
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"4: add %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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" .subsection 2\n"
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"2: ldsw [%2], %0\n"
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" brlz,pt %0, 2b\n"
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" nop\n"
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" ba,a,pt %%xcc, 4b\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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}
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static int inline arch_read_trylock(arch_rwlock_t *lock)
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{
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int tmp1, tmp2;
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__asm__ __volatile__ (
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"1: ldsw [%2], %0\n"
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" brlz,a,pn %0, 2f\n"
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" mov 0, %0\n"
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" add %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%icc, 1b\n"
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" mov 1, %0\n"
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"2:"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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return tmp1;
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}
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static void inline arch_read_unlock(arch_rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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"1: lduw [%2], %0\n"
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" sub %0, 1, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%xcc, 1b\n"
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" nop"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock)
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: "memory");
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}
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static void inline arch_write_lock(arch_rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2;
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mask = 0x80000000UL;
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__asm__ __volatile__(
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"1: lduw [%2], %0\n"
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" brnz,pn %0, 2f\n"
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"4: or %0, %3, %1\n"
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" cas [%2], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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" .subsection 2\n"
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"2: lduw [%2], %0\n"
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" brnz,pt %0, 2b\n"
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" nop\n"
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" ba,a,pt %%xcc, 4b\n"
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" .previous"
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: "=&r" (tmp1), "=&r" (tmp2)
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: "r" (lock), "r" (mask)
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: "memory");
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}
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static void inline arch_write_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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" stw %%g0, [%0]"
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: /* no outputs */
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: "r" (lock)
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: "memory");
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}
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static int inline arch_write_trylock(arch_rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2, result;
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mask = 0x80000000UL;
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__asm__ __volatile__(
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" mov 0, %2\n"
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"1: lduw [%3], %0\n"
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" brnz,pn %0, 2f\n"
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" or %0, %4, %1\n"
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" cas [%3], %0, %1\n"
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" cmp %0, %1\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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" mov 1, %2\n"
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"2:"
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: "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
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: "r" (lock), "r" (mask)
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: "memory");
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return result;
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}
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#define arch_read_lock_flags(p, f) arch_read_lock(p)
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#define arch_write_lock_flags(p, f) arch_write_lock(p)
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#define arch_read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
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#define arch_write_can_lock(rw) (!(rw)->lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC64_SPINLOCK_H) */
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