d8dcbdd08c
The mode constants are taken from the GPL-2.0+ driver available in the driver section of the Moxa homepage. It is tested on a C320Turbo PCI card per logic analyzer and per a device which requires 9 bit character communication. The vendors driver supports CMSPAR unconditionally, so that all other available firmware versions seems to support mark/space parity modes as well. Signed-off-by: Lars Kanis <kanis@comcard.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
307 lines
8.5 KiB
C
307 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef MOXA_H_FILE
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#define MOXA_H_FILE
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#define MOXA 0x400
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#define MOXA_GET_IQUEUE (MOXA + 1) /* get input buffered count */
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#define MOXA_GET_OQUEUE (MOXA + 2) /* get output buffered count */
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#define MOXA_GETDATACOUNT (MOXA + 23)
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#define MOXA_GET_IOQUEUE (MOXA + 27)
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#define MOXA_FLUSH_QUEUE (MOXA + 28)
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#define MOXA_GETMSTATUS (MOXA + 65)
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/*
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* System Configuration
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*/
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#define Magic_code 0x404
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/*
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* for C218 BIOS initialization
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*/
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#define C218_ConfBase 0x800
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#define C218_status (C218_ConfBase + 0) /* BIOS running status */
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#define C218_diag (C218_ConfBase + 2) /* diagnostic status */
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#define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
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#define C218DLoad_len (C218_ConfBase + 6) /* WORD */
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#define C218check_sum (C218_ConfBase + 8) /* BYTE */
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#define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
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#define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
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#define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
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#define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
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#define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
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#define C218_LoadBuf 0x0F00
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#define C218_KeyCode 0x218
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#define CP204J_KeyCode 0x204
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/*
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* for C320 BIOS initialization
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*/
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#define C320_ConfBase 0x800
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#define C320_LoadBuf 0x0f00
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#define STS_init 0x05 /* for C320_status */
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#define C320_status C320_ConfBase + 0 /* BIOS running status */
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#define C320_diag C320_ConfBase + 2 /* diagnostic status */
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#define C320_key C320_ConfBase + 4 /* WORD (0320H for C320) */
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#define C320DLoad_len C320_ConfBase + 6 /* WORD */
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#define C320check_sum C320_ConfBase + 8 /* WORD */
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#define C320chksum_ok C320_ConfBase + 0x0a /* WORD (1:ok) */
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#define C320bapi_len C320_ConfBase + 0x0c /* WORD */
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#define C320UART_no C320_ConfBase + 0x0e /* WORD */
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#define C320_KeyCode 0x320
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#define FixPage_addr 0x0000 /* starting addr of static page */
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#define DynPage_addr 0x2000 /* starting addr of dynamic page */
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#define C218_start 0x3000 /* starting addr of C218 BIOS prg */
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#define Control_reg 0x1ff0 /* select page and reset control */
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#define HW_reset 0x80
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/*
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* Function Codes
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*/
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#define FC_CardReset 0x80
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#define FC_ChannelReset 1 /* C320 firmware not supported */
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#define FC_EnableCH 2
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#define FC_DisableCH 3
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#define FC_SetParam 4
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#define FC_SetMode 5
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#define FC_SetRate 6
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#define FC_LineControl 7
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#define FC_LineStatus 8
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#define FC_XmitControl 9
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#define FC_FlushQueue 10
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#define FC_SendBreak 11
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#define FC_StopBreak 12
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#define FC_LoopbackON 13
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#define FC_LoopbackOFF 14
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#define FC_ClrIrqTable 15
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#define FC_SendXon 16
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#define FC_SetTermIrq 17 /* C320 firmware not supported */
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#define FC_SetCntIrq 18 /* C320 firmware not supported */
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#define FC_SetBreakIrq 19
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#define FC_SetLineIrq 20
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#define FC_SetFlowCtl 21
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#define FC_GenIrq 22
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#define FC_InCD180 23
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#define FC_OutCD180 24
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#define FC_InUARTreg 23
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#define FC_OutUARTreg 24
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#define FC_SetXonXoff 25
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#define FC_OutCD180CCR 26
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#define FC_ExtIQueue 27
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#define FC_ExtOQueue 28
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#define FC_ClrLineIrq 29
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#define FC_HWFlowCtl 30
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#define FC_GetClockRate 35
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#define FC_SetBaud 36
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#define FC_SetDataMode 41
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#define FC_GetCCSR 43
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#define FC_GetDataError 45
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#define FC_RxControl 50
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#define FC_ImmSend 51
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#define FC_SetXonState 52
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#define FC_SetXoffState 53
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#define FC_SetRxFIFOTrig 54
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#define FC_SetTxFIFOCnt 55
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#define FC_UnixRate 56
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#define FC_UnixResetTimer 57
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#define RxFIFOTrig1 0
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#define RxFIFOTrig4 1
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#define RxFIFOTrig8 2
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#define RxFIFOTrig14 3
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/*
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* Dual-Ported RAM
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*/
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#define DRAM_global 0
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#define INT_data (DRAM_global + 0)
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#define Config_base (DRAM_global + 0x108)
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#define IRQindex (INT_data + 0)
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#define IRQpending (INT_data + 4)
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#define IRQtable (INT_data + 8)
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/*
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* Interrupt Status
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*/
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#define IntrRx 0x01 /* receiver data O.K. */
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#define IntrTx 0x02 /* transmit buffer empty */
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#define IntrFunc 0x04 /* function complete */
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#define IntrBreak 0x08 /* received break */
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#define IntrLine 0x10 /* line status change
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for transmitter */
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#define IntrIntr 0x20 /* received INTR code */
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#define IntrQuit 0x40 /* received QUIT code */
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#define IntrEOF 0x80 /* received EOF code */
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#define IntrRxTrigger 0x100 /* rx data count reach tigger value */
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#define IntrTxTrigger 0x200 /* tx data count below trigger value */
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#define Magic_no (Config_base + 0)
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#define Card_model_no (Config_base + 2)
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#define Total_ports (Config_base + 4)
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#define Module_cnt (Config_base + 8)
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#define Module_no (Config_base + 10)
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#define Timer_10ms (Config_base + 14)
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#define Disable_IRQ (Config_base + 20)
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#define TMS320_PORT1 (Config_base + 22)
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#define TMS320_PORT2 (Config_base + 24)
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#define TMS320_CLOCK (Config_base + 26)
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/*
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* DATA BUFFER in DRAM
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*/
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#define Extern_table 0x400 /* Base address of the external table
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(24 words * 64) total 3K bytes
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(24 words * 128) total 6K bytes */
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#define Extern_size 0x60 /* 96 bytes */
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#define RXrptr 0x00 /* read pointer for RX buffer */
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#define RXwptr 0x02 /* write pointer for RX buffer */
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#define TXrptr 0x04 /* read pointer for TX buffer */
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#define TXwptr 0x06 /* write pointer for TX buffer */
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#define HostStat 0x08 /* IRQ flag and general flag */
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#define FlagStat 0x0A
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#define FlowControl 0x0C /* B7 B6 B5 B4 B3 B2 B1 B0 */
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/* x x x x | | | | */
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/* | | | + CTS flow */
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/* | | +--- RTS flow */
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/* | +------ TX Xon/Xoff */
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/* +--------- RX Xon/Xoff */
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#define Break_cnt 0x0E /* received break count */
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#define CD180TXirq 0x10 /* if non-0: enable TX irq */
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#define RX_mask 0x12
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#define TX_mask 0x14
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#define Ofs_rxb 0x16
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#define Ofs_txb 0x18
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#define Page_rxb 0x1A
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#define Page_txb 0x1C
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#define EndPage_rxb 0x1E
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#define EndPage_txb 0x20
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#define Data_error 0x22
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#define RxTrigger 0x28
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#define TxTrigger 0x2a
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#define rRXwptr 0x34
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#define Low_water 0x36
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#define FuncCode 0x40
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#define FuncArg 0x42
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#define FuncArg1 0x44
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#define C218rx_size 0x2000 /* 8K bytes */
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#define C218tx_size 0x8000 /* 32K bytes */
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#define C218rx_mask (C218rx_size - 1)
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#define C218tx_mask (C218tx_size - 1)
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#define C320p8rx_size 0x2000
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#define C320p8tx_size 0x8000
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#define C320p8rx_mask (C320p8rx_size - 1)
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#define C320p8tx_mask (C320p8tx_size - 1)
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#define C320p16rx_size 0x2000
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#define C320p16tx_size 0x4000
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#define C320p16rx_mask (C320p16rx_size - 1)
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#define C320p16tx_mask (C320p16tx_size - 1)
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#define C320p24rx_size 0x2000
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#define C320p24tx_size 0x2000
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#define C320p24rx_mask (C320p24rx_size - 1)
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#define C320p24tx_mask (C320p24tx_size - 1)
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#define C320p32rx_size 0x1000
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#define C320p32tx_size 0x1000
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#define C320p32rx_mask (C320p32rx_size - 1)
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#define C320p32tx_mask (C320p32tx_size - 1)
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#define Page_size 0x2000U
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#define Page_mask (Page_size - 1)
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#define C218rx_spage 3
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#define C218tx_spage 4
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#define C218rx_pageno 1
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#define C218tx_pageno 4
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#define C218buf_pageno 5
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#define C320p8rx_spage 3
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#define C320p8tx_spage 4
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#define C320p8rx_pgno 1
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#define C320p8tx_pgno 4
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#define C320p8buf_pgno 5
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#define C320p16rx_spage 3
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#define C320p16tx_spage 4
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#define C320p16rx_pgno 1
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#define C320p16tx_pgno 2
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#define C320p16buf_pgno 3
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#define C320p24rx_spage 3
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#define C320p24tx_spage 4
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#define C320p24rx_pgno 1
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#define C320p24tx_pgno 1
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#define C320p24buf_pgno 2
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#define C320p32rx_spage 3
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#define C320p32tx_ofs C320p32rx_size
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#define C320p32tx_spage 3
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#define C320p32buf_pgno 1
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/*
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* Host Status
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*/
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#define WakeupRx 0x01
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#define WakeupTx 0x02
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#define WakeupBreak 0x08
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#define WakeupLine 0x10
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#define WakeupIntr 0x20
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#define WakeupQuit 0x40
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#define WakeupEOF 0x80 /* used in VTIME control */
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#define WakeupRxTrigger 0x100
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#define WakeupTxTrigger 0x200
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/*
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* Flag status
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*/
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#define Rx_over 0x01
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#define Xoff_state 0x02
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#define Tx_flowOff 0x04
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#define Tx_enable 0x08
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#define CTS_state 0x10
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#define DSR_state 0x20
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#define DCD_state 0x80
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/*
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* FlowControl
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*/
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#define CTS_FlowCtl 1
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#define RTS_FlowCtl 2
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#define Tx_FlowCtl 4
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#define Rx_FlowCtl 8
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#define IXM_IXANY 0x10
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#define LowWater 128
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#define DTR_ON 1
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#define RTS_ON 2
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#define CTS_ON 1
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#define DSR_ON 2
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#define DCD_ON 8
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/* mode definition */
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#define MX_CS8 0x03
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#define MX_CS7 0x02
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#define MX_CS6 0x01
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#define MX_CS5 0x00
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#define MX_STOP1 0x00
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#define MX_STOP15 0x04
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#define MX_STOP2 0x08
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#define MX_PARNONE 0x00
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#define MX_PAREVEN 0x40
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#define MX_PARODD 0xC0
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#define MX_PARMARK 0xA0
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#define MX_PARSPACE 0x20
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#endif
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