517af33237
This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| fault.c | ||
| generic.c | ||
| hugetlbpage.c | ||
| init.c | ||
| Makefile | ||
| tlb.c | ||
| tsb.c | ||
| ultra.S | ||