Suresh Siddha cd7240c0b9 x86, tsc, sched: Recompute cyc2ns_offset's during resume from sleep states ... TSC's get reset after suspend/resume (even on cpu's with invariant TSC which runs at a constant rate across ACPI P-, C- and T-states). And in some systems BIOS seem to reinit TSC to arbitrary large value (still sync'd across cpu's) during resume. This leads to a scenario of scheduler rq->clock (sched_clock_cpu()) less than rq->age_stamp (introduced in 2.6.32). This leads to a big value returned by scale_rt_power() and the resulting big group power set by the update_group_power() is causing improper load balancing between busy and idle cpu's after suspend/resume. This resulted in multi-threaded workloads (like kernel-compilation) go slower after suspend/resume cycle on core i5 laptops. Fix this by recomputing cyc2ns_offset's during resume, so that sched_clock() continues from the point where it was left off during suspend. Reported-by: Florian Pritz <flo@xssn.at> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: <stable@kernel.org> # [v2.6.32+] Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1282262618.2675.24.camel@sbsiddha-MOBL3.sc.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>		2010-08-20 14:59:02 +02:00
..
cpu.c	x86, tsc, sched: Recompute cyc2ns_offset's during resume from sleep states	2010-08-20 14:59:02 +02:00
hibernate_32.c
hibernate_64.c	update email address	2010-07-19 10:56:54 +02:00
hibernate_asm_32.S	x86-32, resume: do a global tlb flush in S4 resume	2010-03-30 11:46:02 -07:00
hibernate_asm_64.S
Makefile